Handbook of Computer Architecture

Recent advances in different instruction set architectures (ISAs) and their implementations have revived the argument on the role of ISAs in the overall performance and energy efficiency of a processor. Many computer architects believe that with current compiler and microarchitecture developments, the choice of ISA is not a decisive matter anymore. On the other hand, some believe that ISAs can still play an important role in the overall performance and energy efficiency of a computer system. Our objective is to compare and contrast ISAs by finding the differences in performance and energy consumption across ISAs and the reasons behind those differences. Our work shows that ISAs affect the performance and energy efficiency of applications differently based on their inherent characteristics.

To the present day, the performance of microprocessors has progressed dramatically. Recently, almost all computer systems use reduced instruction set computer (RISC) architectures. However, about 30 years ago, complex instruction set computer (CISC) architectures were widely used for almost all computer systems. The advantages and successes of RISC architectures are attributable to their simplified structures. Conventional complex instruction set computer (CISC) architectures invariably included various and numerous instruction sets. Each instruction was able to execute a complicated multi-step operation. For that reason, the CISC architectures were useful in assembler-based programming environments and in systems with small amounts of memory. However, such complicated architectures prevent increases in clock frequency or a processor’s processing power. Therefore, RISC architectures—which use simple architectures based on single-step instruction sets—have been developed. The RISC architectures present advantages in terms of higher clock frequency, smaller implementation area, and lower power consumption than conventional complex instruction set computer (CISC) architectures. Observation of many examples reveals that, in circuit implementations, a simple structure is best to increase the overall performance. That principle is also applicable to programmable devices. If clock-by-clock reconfigurable devices are used, even a single instruction set computer (SISC) can be implemented onto them. A single instruction set computer is one in which a processor has only a single instruction. During production, various single instruction set computers are prepared: a single instruction set computer with an AND logic function, a single instruction set computer with an adder function, and so on. These processor units are implemented at necessary times and at necessary places of a programmable device. In CISC and RISC architectures, the hardware is fixed. Its operations are switched using software commands, as portrayed in Fig. 1(a). In contrast, in a single instruction set computer, the operation changes are executed by hardware reconfigurations, as shown in Figs. 1(b) and 1(c). Therefore, in a single instruction set computer, a processor with a certain function itself can be reconfigured to another processor with another function. The implementation of such single instruction set computers provides the following advantages under programmable device implementations. A single instruction set computer with the simplest architecture can operate at the highest clock frequency among all processor architectures. In RISC architectures, many selectors to change functions are implemented; such selectors have a certain delay. However, single instruction set computers

Carbon capture and storage (CCS) technologies represent a critical strategic intervention in addressing global climate change challenges while maintaining energy security in natural gas infrastructure. This comprehensive review explores the multifaceted landscape of CCS technologies, examining technological innovations, economic frameworks, and environmental implications for clean energy production. By synthesizing current research and emerging approaches, the study provides a holistic assessment of CCS potential in mitigating carbon emissions from natural gas facilities. The review critically analyzes existing capture technologies, including post-combustion, pre-combustion, and oxy-fuel combustion methods, highlighting recent advances in material sciences and technological innovations. Economic considerations are examined through the lens of investment strategies, policy frameworks, and long-term viability. Environmental performance evaluation encompasses comprehensive emissions assessment, geological storage risks, and broader ecosystem implications. Key findings underscore the complexity of CCS implementation, revealing both significant challenges and promising opportunities for transforming natural gas infrastructure. The study emphasizes the need for interdisciplinary approaches, robust policy support, and continued technological innovation to realize the full potential of carbon capture technologies in achieving sustainable energy transitions.

Code execution in modern superscalar processors is inherently redundant. Many instructions execute repeatedly with the same inputs, producing the same outputs, thus wasting resources in the process. Value reuse techniques memorize previous executions of instructions, blocks or traces which may be reused if they appear again with the same input contexts. Although trace reuse techniques show great potential for both performance and energy consumption improvement, they have not been studied yet in one of the most widely available computer architectures - the ARM architecture. In this paper, the main issues with reusing traces in instruction sets with conditional execution are revisited. Afterwards, the reuse potential in the benchmark suite MiBench is analyzed varying (i) how traces are generated, and (ii) the size of reuse tables. Our results show that a memoization table of 32 KiB allows to reuse 18.36% of the total instructions on average.

This paper presents two computer architecture mechanisms that can be employed together to allow programs to be written where their individual instructions can (1) be executed in parallel in separate processors and (2) be arbitrarily assigned to be executed by any processor in a connected fabric of processors. This is an emerging parallel execution technique for future high performance and embedded computers. Changing the placement of a program's instructions in a processing fabric is equivalent to rearranging the computer architecture around the program itself. Reasons to change the computer architecture around the software are to improve overall execution speed and to perform load balancing. The two computer architecture mechanisms are (1) a custom dataflow instruction set and (2) a processor block called an operation cell. The most important feature of the instruction set is the high level of operational independence of the instructions (i.e. no shared memory/registers between instructions). The operation cell is a processor construct that stores an instruction and manages the execution life of that instruction. An operation cell either executes the instruction itself or forwards the execution to another operation cell in a different processor.

Computer systems courses, including computer organization, architecture, operating system, compiler, and other relevant courses, play an important role in cultivating students' computational thinking, especially the ability of viewing hardware and software in a computer system as a whole. In order to help learners to better understand principles and concepts taught in lectures of aforementioned courses, some visionary instructors have started to design lab projects for their courses with real-world instruction set architectures (ISAs), such as MIPS, ARM and x86, or even request students to conduct projects on these ISAs-based hardware platforms. Meanwhile, with the overwhelming trend towards AI, IoT and heterogeneous computing, RISC-V, an open and free ISA, has emerged and recently attracted a lot of attention from both academia and industry. Compared with proprietary ISAs, RISC-V is more simple, affordable, extensible and compatible. Given this context, several arising questions can be examined and discussed in this BoF session. For example, 1) whether the computer systems courses should integrate RISC-V, 2) do we need minor (evolutionary) or major (revolutionary) curriculum changes with the involvement of RISC-V for each course or the entire CS curriculum, 3) how to help the majority of students accommodate to these changes, 4) what kind of new course materials should be provided to instructors, TAs and students, 5) whether it's possible for some senior students to tape-out their own RISC-V chip designs and finally produce a cornucopia of workable computing systems with this revolutionary and open curriculum.

This study is concerned with measurements of the characteristics of current use of digital computer instruction sets, and an analysis of those measurements to produce conclusions useful for future design evaluation. The results include conclusions about computer architectures and their implementations. In order to apportion the time spent by an executing program among the various system components, a model of high-performance computers is derived from instruction timing formulas, with compensation for pipeline and cache memory effects. The model is used to predict the performance of the IBM 370/168 and the Amdahl 470 V/6 on specific programs, and the results are verified by comparison with actual performance. Measurements are made and discussed for other instruction set architectures, including a current microprocessor (the INTEL 8080), a popular minicomputer (the DEC PDP11), and a pseudo-computer used as an intermediate step for PASCAL compilation or interpretation. Some predictive models are investigated. An improved mechanism for conditional branch prediction is proposed and simulated. The performance of a radically different implementation of the 370 is examined and its performance is predicted. Finally, some of the data gathered is used as the basis for a model of the instruction fetch process; that model is solved analytically. Design rules which should be followed to allow instruction sets to be implemented with high-performance processors are given. 27 figures, 24 tables.

A legend in computer architecture and perhaps best known as a pioneer of ideas that led to reduced instruction set computing, John Cocke has designed machines that still influence processor design today. In conjunction with his winning the inaugural Seymour Cray award, Computer interviewed Cocke in his Westchester, New York, home. Computer talked to Cocke about how he became interested in computers and the projects for which he is famous: the IBM Stretch, Advanced Computer System (ACS), and the 801, RS6000, and PowerPC processors. The project to build the 801 (one of the first RISC processors) used the code-name America. Cocke recounts how he chose the name based on a story about the first America's Cup yacht race. In the interview, Cocke expresses his opinions on the prospects for parallel computing, quantum computing, and future computer architectures.

In today’s technological landscape, embedded and IoT devices face escalating demands for performance and power efficiency in inference tasks employing Convolution Neural Networks (CNNs). Various methods have emerged to improve performance, including quantization and the adoption of fixed-point formats instead of floating-point formats. RISC-V Instruction Set Architecture (ISA) being open-source and with a modular specification poses as a suitable platform for targeting such applications for embedded processing. The RISC-V’s standard P-extension represents a significant advancement in integer-based computation, offering new ways for achieving higher speedups through integer-packed SIMD instructions. This work presents the first RISC-V processor based on RV32IM base ISA with an optional support of P-extension Version 0.9.11-draft-20211209 called the P-CORE. The P-CORE implements P-extension ISA for RV32 specification. The implemented processor is evaluated for Xilinx Zynq Ultrascale+ FPGA using different test case functions; matrix multiplication, convolution, max-pooling, and fully connected. A CNN used for detecting handwritten digits called Lenet-5 is also used as a test case to evaluate the P-CORE. The evaluation also presents Design Space Exploration (DSE) for P-extension by exploiting the level of data-level-parallelism; SIMD8 (8-bit (4-way)) and SIMD16 (16-bit (2-way)). Our investigation demonstrates that with the P-extension activated, CNN algorithm computations can achieve speedups of up to 17x for max-pooling, 7x for matrix multiplication, and 4.8x for fully connected networks, accompanied by similar enhancements in power efficiency. The processor achieved a maximum performance of 335.1 MIOPS and 490.6 MIOPS/W efficiency for matrix multiplication using -O3 compiler optimization.

Students learn better when they both hear and do. In computer architecture courses “doing” can be difficult in small schools without hardware laboratories hosted by computer engineering, electrical engineering, or similar departments. Software solutions exist. Our success with George Mills' Multimedia Logic (MML) is the focus of this paper. MML provides a graphical computer architecture solution with convenient I/O support and the ability to build and emulate a variety of computer designs. It has proven highly motivational to upper division computer science students designing and constructing emulated computers. Student projects resulted in excellent student understanding of the detailed inner workings of computers. Students also developed better teamwork skills and produced useful training aids for the lower division computer organization class. Designs implemented include 8 bit and 16 bit von Neumann and Harvard architectures, from single cycle to 12 cycle instructions. Issues resolved during the learning process include timing, initialization, instruction set architecture, and I/O and assembler design. We discuss pedagogical issues involved in using MML to implement instructor and student computer designs. MML is compared to using a hardware-based Intel 8085 microprocessor basic systems course.

Implementation of heat production and storage technology and devices in power systems

Control-flow computer architectures are based on the von Neumann paradigm. They are flexible enough to support the execution of instructions in any order. Each instruction is fetched from the memory before it could be executed. Passing the data from the instruction that produces it to the instruction that requires it is done using registers or memory. DataFlow computer architectures are configured for execution of an algorithm, while data travel through the hardware. They are suitable for high-performance computing, where the same set of instructions should be run many times. Initialization of data and other processing is done by the processor based on control-flow. The Maxeler framework provides functionality for transforming any algorithm into a VHDL file, and further configuring the dataflow hardware. It also provides support for sending data from the control-flow host processor to the dataflow hardware, and bringing results back. Common programming languages are supported for the host processor, while dataflow hardware programming is done in MaxJ, which is an extended subset of the Java programming language. One can use an integrated development environment called MaxIDE, which is based on Eclipse. We present here a perspective overview of a cloud-supported web-based integrated development environment, WebIDE, which is a subset of MaxIDE, and enables users to develop and run programs for dataflow hardware even without owning dataflow hardware. The main concepts are explained, as well as differences in two integrated development environments. Then, our main focus is on the point of view of programmers, and the goal is to compare the MaxIDE and the WebIDE Maxeler framework, describing the technology needed to support the WebIDE Maxeler framework, providing that the MaxIDE already exists.

Cross-ISA system-mode emulation has many important applications. For example, Cross-ISA system-mode emulation helps computer architects and OS developers trace and debug kernel execution-flow efficiently by emulating a slower platform (such as ARM) on a more powerful plat-form (such as an x86 machine). Cross-ISA system-mode emulation also enables workload consolidation in data centers with platforms of different instruction-set architectures (ISAs). However, system-mode emulation is much slower. One major overhead in system-mode emulation is the multi-level memory address translation that maps guest virtual address to host physical address. Shadow page tables (SPT) have been used to reduce such overheads, but primarily for same-ISA virtualization. In this paper we propose a novel approach called embedded shadow page tables (ESPT). EPST embeds a shadow page table into the address space of a cross-ISA dynamic binary translation (DBT) and uses hardware memory management unit in the CPU to translate memory addresses, instead of software translation in a current DBT emulator like QEMU. We also use the larger address space on modern 64-bit CPUs to accommodate our DBT emulator so that it will not interfere with the guest operating system. We incorporate our new scheme into QEMU, a popular, retargetable cross-ISA system emulator. SPEC CINT2006 benchmark results indicate that our technique achieves an average speedup of 1.51 times in system mode when emulating ARM on x86, and a 1.59 times speedup for emulating IA32 on x86_64.

Designing a NICE processor

An object-oriented approach to modeling and simulation computer architectures is presented. Rather than concentrating on a specific system, the more generic concepts of processors, memories, clocks, registers, instruction sets, etc. are developed. By building upon these basic concepts, it is then possible to simulate virtually any processor to nearly any level of detail.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>