Value Reuse Potential in ARM Architectures

Recent advances in different instruction set architectures (ISAs) and their implementations have revived the argument on the role of ISAs in the overall performance and energy efficiency of a processor. Many computer architects believe that with current compiler and microarchitecture developments, the choice of ISA is not a decisive matter anymore. On the other hand, some believe that ISAs can still play an important role in the overall performance and energy efficiency of a computer system. Our objective is to compare and contrast ISAs by finding the differences in performance and energy consumption across ISAs and the reasons behind those differences. Our work shows that ISAs affect the performance and energy efficiency of applications differently based on their inherent characteristics.

Chapter 11 - The ARM Architecture

Fault Injection for Linux Device Drivers on x86, MIPS and ARM Architectures

To the present day, the performance of microprocessors has progressed dramatically. Recently, almost all computer systems use reduced instruction set computer (RISC) architectures. However, about 30 years ago, complex instruction set computer (CISC) architectures were widely used for almost all computer systems. The advantages and successes of RISC architectures are attributable to their simplified structures. Conventional complex instruction set computer (CISC) architectures invariably included various and numerous instruction sets. Each instruction was able to execute a complicated multi-step operation. For that reason, the CISC architectures were useful in assembler-based programming environments and in systems with small amounts of memory. However, such complicated architectures prevent increases in clock frequency or a processor’s processing power. Therefore, RISC architectures—which use simple architectures based on single-step instruction sets—have been developed. The RISC architectures present advantages in terms of higher clock frequency, smaller implementation area, and lower power consumption than conventional complex instruction set computer (CISC) architectures. Observation of many examples reveals that, in circuit implementations, a simple structure is best to increase the overall performance. That principle is also applicable to programmable devices. If clock-by-clock reconfigurable devices are used, even a single instruction set computer (SISC) can be implemented onto them. A single instruction set computer is one in which a processor has only a single instruction. During production, various single instruction set computers are prepared: a single instruction set computer with an AND logic function, a single instruction set computer with an adder function, and so on. These processor units are implemented at necessary times and at necessary places of a programmable device. In CISC and RISC architectures, the hardware is fixed. Its operations are switched using software commands, as portrayed in Fig. 1(a). In contrast, in a single instruction set computer, the operation changes are executed by hardware reconfigurations, as shown in Figs. 1(b) and 1(c). Therefore, in a single instruction set computer, a processor with a certain function itself can be reconfigured to another processor with another function. The implementation of such single instruction set computers provides the following advantages under programmable device implementations. A single instruction set computer with the simplest architecture can operate at the highest clock frequency among all processor architectures. In RISC architectures, many selectors to change functions are implemented; such selectors have a certain delay. However, single instruction set computers

This paper presents two computer architecture mechanisms that can be employed together to allow programs to be written where their individual instructions can (1) be executed in parallel in separate processors and (2) be arbitrarily assigned to be executed by any processor in a connected fabric of processors. This is an emerging parallel execution technique for future high performance and embedded computers. Changing the placement of a program's instructions in a processing fabric is equivalent to rearranging the computer architecture around the program itself. Reasons to change the computer architecture around the software are to improve overall execution speed and to perform load balancing. The two computer architecture mechanisms are (1) a custom dataflow instruction set and (2) a processor block called an operation cell. The most important feature of the instruction set is the high level of operational independence of the instructions (i.e. no shared memory/registers between instructions). The operation cell is a processor construct that stores an instruction and manages the execution life of that instruction. An operation cell either executes the instruction itself or forwards the execution to another operation cell in a different processor.

Computer architectures sit at an important juncture between ever-changing landscape of implementation technology and emerging applications.It presented with a crucial connect between the plane of abstract algorithm and detailed computing and storage technologies -through the lens of Instruction-Set Architectures (ISA) and micro-architecture.Over the years, the architectures evolved to cater to various applications, with the core objective of achieving better runtime, smaller area, and lesser power consumption.This led to pathbreaking innovations, which, in turn catapulted various application segments to prominence, such as wireless/mobile computing, graphics processing, and more recently machine learning.It is a difficult task to capture such momentum with various tributaries in a single volume and yet, this is what is attempted in the current Handbook of Computer Architectures.While the content follows a standard narrative, the format of this book is unique.It offers live update of the content, thereby allowing the authors to include modern developments within the same context of a specific topic.The content is spread over multiple sections, and in each section, specific chapters offer a detailed glimpse of a topic of interest.The chapters are presented in increasing order of advanced concepts.It is also cross-linked in such a manner that reader can peruse a chapter with only necessary pre-requisite from selected, prior chapters.In the first section of single-core processors, three chapters provide the background of computer organization, microarchitecture, and communication networks.This is complemented with chapters on operating systems, edge computing, and secure computing architectures -which provide sufficient foundation for a reader to move toward more advanced notions in any of the following sections.The section on application-specific processors provides valuable insights into the growing demands from application developers to have customized architectures, also referred to as co-processors or accelerators.From a wide range of application segments, multimedia processing, scientific computing, machine learning, and cryptographic workloads are chosen to be covered here.Since these applications heavily depend on digital arithmetic, a short overview of the concepts is presented as well.Multimedia, machine learning, and several other domain-specific architectures are known to get influenced -for good or worse -due to the device-level faults appearing in advanced technology nodes.This is discussed in the section of faulttolerant architectures.

As the performance gap between processor and memory grows, memory latency becomes a major bottleneck in achieving high processor utilization. Multithreading has emerged as one of the most promising and exciting techniques used to tolerate memory latency by exploiting thread-level parallelism. The question, however, remains as to how effective multithreading is on tolerating memory latency. The performance of multithreading is not only affected by the overlapping of memory latency with useful computation, but also strongly depends on the cache behavior and the overhead of multithreading (e.g., thread management and context-switch costs). In particular, multithreading affects the behavior of caches, and, thus, the overall performance in a nontrivial fashion. To study these issues, this paper presents the Multithreaded Virtual Processor (MVP) model. MVP integrates the multithreaded programming paradigm and a modern superscalar processor with support for fast context switching and thread scheduling. Our studies with MVP show that, in general, the performance improvements are obtained not only by tolerating memory latency but also lower cache miss rates due to exploitation of data locality. However, multithreading creates an additional stress on the memory hierarchy caused by the interference among threads. Also, the dynamic behavior of multithreaded execution hinders the instruction locality that results in a high number of misses in the L1 instruction cache.

Computer systems courses, including computer organization, architecture, operating system, compiler, and other relevant courses, play an important role in cultivating students' computational thinking, especially the ability of viewing hardware and software in a computer system as a whole. In order to help learners to better understand principles and concepts taught in lectures of aforementioned courses, some visionary instructors have started to design lab projects for their courses with real-world instruction set architectures (ISAs), such as MIPS, ARM and x86, or even request students to conduct projects on these ISAs-based hardware platforms. Meanwhile, with the overwhelming trend towards AI, IoT and heterogeneous computing, RISC-V, an open and free ISA, has emerged and recently attracted a lot of attention from both academia and industry. Compared with proprietary ISAs, RISC-V is more simple, affordable, extensible and compatible. Given this context, several arising questions can be examined and discussed in this BoF session. For example, 1) whether the computer systems courses should integrate RISC-V, 2) do we need minor (evolutionary) or major (revolutionary) curriculum changes with the involvement of RISC-V for each course or the entire CS curriculum, 3) how to help the majority of students accommodate to these changes, 4) what kind of new course materials should be provided to instructors, TAs and students, 5) whether it's possible for some senior students to tape-out their own RISC-V chip designs and finally produce a cornucopia of workable computing systems with this revolutionary and open curriculum.

This study is concerned with measurements of the characteristics of current use of digital computer instruction sets, and an analysis of those measurements to produce conclusions useful for future design evaluation. The results include conclusions about computer architectures and their implementations. In order to apportion the time spent by an executing program among the various system components, a model of high-performance computers is derived from instruction timing formulas, with compensation for pipeline and cache memory effects. The model is used to predict the performance of the IBM 370/168 and the Amdahl 470 V/6 on specific programs, and the results are verified by comparison with actual performance. Measurements are made and discussed for other instruction set architectures, including a current microprocessor (the INTEL 8080), a popular minicomputer (the DEC PDP11), and a pseudo-computer used as an intermediate step for PASCAL compilation or interpretation. Some predictive models are investigated. An improved mechanism for conditional branch prediction is proposed and simulated. The performance of a radically different implementation of the 370 is examined and its performance is predicted. Finally, some of the data gathered is used as the basis for a model of the instruction fetch process; that model is solved analytically. Design rules which should be followed to allow instruction sets to be implemented with high-performance processors are given. 27 figures, 24 tables.

Nearly 50 years ago, Intel created the world's first commercially produced microprocessor-the 4004 (ref. 1), a modest 4-bit CPU (central processing unit) with 2,300 transistors fabricated using 10μm process technology in silicon and capable only of simple arithmetic calculations. Since this ground-breaking achievement, there has been continuous technological development with increasing sophistication to the stage where state-of-the-art silicon 64-bit microprocessors now have 30 billion transistors (for example, the AWS Graviton2 (ref. 2) microprocessor, fabricated using 7nm process technology). The microprocessor is now so embedded within our culture that it has become a meta-invention-that is, it is a tool that allows other inventions to be realized, most recently enabling the big data analysis needed for a COVID-19 vaccine to be developed in record time. Here we report a 32-bit Arm (a reduced instruction set computing (RISC) architecture) microprocessor developed with metal-oxide thin-film transistor technology on a flexible substrate (which we call the PlasticARM). Separate from the mainstream semiconductor industry, flexible electronics operate within a domain that seamlessly integrates with everyday objects through a combination of ultrathin form factor, conformability, extreme low cost and potential for mass-scale production. PlasticARM pioneers the embedding of billions of low-cost, ultrathin microprocessors into everyday objects.

Control-flow computer architectures are based on the von Neumann paradigm. They are flexible enough to support the execution of instructions in any order. Each instruction is fetched from the memory before it could be executed. Passing the data from the instruction that produces it to the instruction that requires it is done using registers or memory. DataFlow computer architectures are configured for execution of an algorithm, while data travel through the hardware. They are suitable for high-performance computing, where the same set of instructions should be run many times. Initialization of data and other processing is done by the processor based on control-flow. The Maxeler framework provides functionality for transforming any algorithm into a VHDL file, and further configuring the dataflow hardware. It also provides support for sending data from the control-flow host processor to the dataflow hardware, and bringing results back. Common programming languages are supported for the host processor, while dataflow hardware programming is done in MaxJ, which is an extended subset of the Java programming language. One can use an integrated development environment called MaxIDE, which is based on Eclipse. We present here a perspective overview of a cloud-supported web-based integrated development environment, WebIDE, which is a subset of MaxIDE, and enables users to develop and run programs for dataflow hardware even without owning dataflow hardware. The main concepts are explained, as well as differences in two integrated development environments. Then, our main focus is on the point of view of programmers, and the goal is to compare the MaxIDE and the WebIDE Maxeler framework, describing the technology needed to support the WebIDE Maxeler framework, providing that the MaxIDE already exists.

It is widely known that return-oriented programming (ROP) attack can be mounted on x86, ARM and SPARC architectures. However, it remained an open question if ROP was possible on RISC-V, a new and promising free and open instruction set architecture (ISA). In this paper we present a novel ROP technique specific to RISC-V architecture. Our method relies on the processor's saved registers and its function calling convention. We use functional gadgets (that perform primitive operations) ended in a jump instruction to an address held in a saved register. The order of gadgets chaining is given by a novel gadget, which we call the charger gadget, which loads the saved registers with the gadgets? addresses from the stack. We constructed a library of gadgets extracted from the standard Linux libraries. Finally, we evaluated our method by exploiting a buffer-overflow vulnerable application.

A legend in computer architecture and perhaps best known as a pioneer of ideas that led to reduced instruction set computing, John Cocke has designed machines that still influence processor design today. In conjunction with his winning the inaugural Seymour Cray award, Computer interviewed Cocke in his Westchester, New York, home. Computer talked to Cocke about how he became interested in computers and the projects for which he is famous: the IBM Stretch, Advanced Computer System (ACS), and the 801, RS6000, and PowerPC processors. The project to build the 801 (one of the first RISC processors) used the code-name America. Cocke recounts how he chose the name based on a story about the first America's Cup yacht race. In the interview, Cocke expresses his opinions on the prospects for parallel computing, quantum computing, and future computer architectures.

Deep learning has transformed the use of machine learning technologies for the analysis of large experimental datasets. In science, such datasets are typically generated by large-scale experimental facilities, and machine learning focuses on the identification of patterns, trends and anomalies to extract meaningful scientific insights from the data. In upcoming experimental facilities, such as the Extreme Photonics Application Centre (EPAC) in the UK or the international Square Kilometre Array (SKA), the rate of data generation and the scale of data volumes will increasingly require the use of more automated data analysis. However, at present, identifying the most appropriate machine learning algorithm for the analysis of any given scientific dataset is a challenge due to the potential applicability of many different machine learning frameworks, computer architectures and machine learning models. Historically, for modelling and simulation on high-performance computing systems, these issues have been addressed through benchmarking computer applications, algorithms and architectures. Extending such a benchmarking approach and identifying metrics for the application of machine learning methods to open, curated scientific datasets is a new challenge for both scientists and computer scientists. Here, we introduce the concept of machine learning benchmarks for science and review existing approaches. As an example, we describe the SciMLBench suite of scientific machine learning benchmarks. Finding the most appropriate machine learning algorithm for the analysis of any given scientific dataset is currently challenging, but new machine learning benchmarks for science are being developed to help.

Students learn better when they both hear and do. In computer architecture courses “doing” can be difficult in small schools without hardware laboratories hosted by computer engineering, electrical engineering, or similar departments. Software solutions exist. Our success with George Mills' Multimedia Logic (MML) is the focus of this paper. MML provides a graphical computer architecture solution with convenient I/O support and the ability to build and emulate a variety of computer designs. It has proven highly motivational to upper division computer science students designing and constructing emulated computers. Student projects resulted in excellent student understanding of the detailed inner workings of computers. Students also developed better teamwork skills and produced useful training aids for the lower division computer organization class. Designs implemented include 8 bit and 16 bit von Neumann and Harvard architectures, from single cycle to 12 cycle instructions. Issues resolved during the learning process include timing, initialization, instruction set architecture, and I/O and assembler design. We discuss pedagogical issues involved in using MML to implement instructor and student computer designs. MML is compared to using a hardware-based Intel 8085 microprocessor basic systems course.