Analysis of Guess and Determined Attack on Non Linear Modified SNOW 2.0 Using One LFSR

Communication security that depends on chaos can be considered as a new approach which provides protection and security of communications and maintains confidentiality because Chaos theory can be implemented in cryptosystem successfully. A stream cipher, on the other hand, is a type of symmetric cryptosystem in which the plaintext is divided into small entities known as characters. The key in stream cipher is typically generated by a random bit generator. Many key stream generators employ linear feedback shift registers (LFSRs). LFSR systems are made up of a group of LFSR units and a combining function (CF) unit. The plaintext is encrypted one bit at a time. The key is fed into a random bit generator, which produces a long series of binary signals. This "key-stream" k is then combined with plaintext m, typically via a bit-wise XOR (Exclusive-OR modulo 2 addition), to produce the ciphertext stream, which employs the same random bit generator and seed. In this paper we will introduce a new stream cipher keygenerator which using a hybrid between chaotic and combination of Linear Feedback Shift Registers (LFSR's). The proposed generator can be used to protect different types of data files (text, image, audio and video). Many kinds of tests are applied to specifying the goodness of the proposed keygenerator. The results of testing prove the efficiency of the suggested system.

The stream cipher, a type of secret‐key cipher, gives the key to a pseudorandom number generator and generates a pseudorandom sequence called the key sequence, and generates the ciphertext sequence taking the exclusive‐or of this sequence and the plaintext sequence. A nonlinear combiner generator is a type of pseudorandom number generator used by stream ciphers and is configured from multiple linear‐feedback shift registers (LFSRs) and one nonlinear function. A correlation attack is a method for attacking this type of pseudorandom number generator. The correlation between the output sequence of an LFSR and the key sequence is used to estimate the initial state of the LFSR. However, a conventional attack method attacks a single LFSR and is used only to estimate a portion of the multidimensional correlations of the multiple LFSR sequences and the key sequence. Therefore, we propose an algorithm that improves the attack method using the belief propagation (BP) algorithm of Mihaljević and colleagues and simultaneously attacks multiple LFSRs using the multidimensional correlation. By increasing the information used in the estimation, an improvement in the decoding success rate is expected. In addition, the computational load of the estimation increases, but this increase can be suppressed by an approximation based on the parallel BP algorithm. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 90(4): 9 – 17, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20270

In this paper, new method have been investigated using evolving algorithms (EA's) to cryptanalysis one of the nonlinear stream cipher cryptosystems which depends on the Linear Feedback Shift Register (LFSR) unit by using cipher text-only attack. Genetic Algorithm (GA) and Ant Colony Optimization (ACO) which are used for attacking one of the nonlinear cryptosystems called "shrinking generator" using different lengths of cipher text and different lengths of combined LFSRs. GA and ACO proved their good performance in finding the initial values of the combined LFSRs. This work can be considered as a warning for a stream cipher designer to avoid the weak points, which may be found in the stream cipher, and may be explored by the cryptanalysts. This work can find the optimal solution for text with minimum lengths of 20 characters and 100 iteration were very enough to find the real initial values of key stream.

To obtain satisfactory fault coverage for testing a logic circuit, linear feedback shift registers (LFSRs) have been used to generate not only the pseudorandom, but also the deterministic patterns in the scan-based built-in self-test environment. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time to feed deterministic patterns from the LFSR into a scan chain. In this paper we derive a general relationship between the bits in the scan chain and the states of the LFSR and show that any bit to be generated by an LFSR in any future clock cycle can be pre-generated by a linear function of the current LFSR state. With this relationship, we can divide a scan chain into multiple sub-chains and use one LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time for deterministic patterns. Moreover, due to the scan time reduction, test power wasted during the scan operation can also be significantly reduced.

When Lagged Fibonacci Generators jump

At Indocrypt’2002, a new pseudorandom generator based on linear feedback shift register (LFSR) and feedback with carry shift registers (FCSR) was proposed by Arnault. And at Indocrypt’2004, Bin Zhang et al. showed that the self-synchronizing stream cipher constructed by Arnault’s pseudorandom generator was extremely weak against a chosen ciphertext attack. In this paper, we show that the synchronizing stream cipher constructed by Arnault’s pseudorandom generator bear good immunities to the attack proposed by Bin Zhang et al., but can not resist the LFSRization attack proposed by Martin Hell and Thomas Johansson. Then we propose a modification to the synchronizing stream cipher, and show that it inherits of the nice statistical properties of the pseudorandom generator and provided a resistant to the known attacks. The new architecture still has high throughput and low implementation cost.

We introduce two new correlation attacks on stream ciphers that make use of non-linearly combined linear feedback shift-registers (LFSRs). The first attack utilises the well-known Lempel-Ziv complexity measure for binary sequences. The second attack is based on the binary derivative, applied in conjunction with the distribution of runs in a binary sequence. Both attacks make use of ciphertext only, and give very good results. They are able to recover the unknown (secret) initial state of an internal LFSR, even when only a very small correlation of q=0.52 occurs between the observed ciphertext and the output of an internal LFSR, and approximately 60000 ciphertext bits are required for attacks to succeed. The computational complexity and memory requirements of the binary derivative attack are substantially lower than for the Lempel-Ziv attack, making It feasible to attack stream ciphers with LFSR-lengths of approximately 40 to 50 bits.

In this paper, a 4-bit Linear Feedback Shift Register (LFSR) is implemented based on a well-designed architecture combining using Pass-Transistor (PT) and Clock Complementary Metal Oxide Semiconductor (C2MOS) logic techniques. The D-flip flop registers and the XOR gates are the main parts of the propose LFSR. Number of transistors along with the speed of LFSR were positively enhanced since the exploited logic design techniques tends to blend the flavor of NMOS and PMOS devices. The PSpice and Field Programmable Gate Array (FPGA) based on Hardware Description Language (HDL) are the two different LFSR implementation environments. It has been observed that LFSR performance was effectively improved in terms of size and speed. Therefore, paper’s main aim refers to decreasing in number of transistors as well as speeding up LFSR circuit. A minimum clock time of 5ns was recorded under clearly correct LFSR output patterns. The LFSR circuit Based CMOS techniques can reduce the exploited transistors up to 43% of the conventional C2MOS logic. Besides, the number of transistors being reduced reflects the achieved circuit’s size reduction. It was concluded that paying attention to the design of the main LFSR circuit parts contributes mainly in the enhancement of the whole circuit performance.

Many Built-in Self Test (BIST) pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs of patterns for delay faults testing with LFSRs. A new synthesis procedure for a n-size LFSR is given and guarantees that a deterministic set of n precomputed test pairs is embedded in the maximal length pseudo-random test sequence of the LFSR. Sufficient and necessary conditions for the synthesis of this pseudo-deterministic LFSR are provided and show that at-speed delay faults testing becomes a reality without any additional cost for the LFSR. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other technique proposed so far.

Enhancements of a clock-controlled running key generator

Pseudonoise sequences generated by linear feedback shift registers [1] with some nonlinear combining function have been proposed [2]–[5] for cryptographic applications as running key generators in stream ciphers. In this correspondence it will be shown that the number of trials to break these ciphers can be significantly reduced by using correlation methods. By comparison of computer simulations and theoretical results based on a statistical model, the validity of this analysis is demonstrated. Rubin [6] has shown that it is computationally feasible to solve a cipher proposed by Pless [2] in a known plaintext attack, using as few as 15 characters. Here, the number of ciphertext symbols is determined to perform a ciphertext-only attack on the Pless cipher using the correlation attack. Our conclusion from the analysis is that the pseudonoise generator's output sequence and the sequences generated by the linear feedback shift registers should be uncorrelated. This leads to constraints for the nonlinear combining function to be used.

Linear feedback shift register (LFSR) is an important part of sequence cipher. In this paper, we introduce a kind of reconfigurable LFSR design. According to need, it can be configured to be a random LFSR to run over GF (2), GF (2^8) ,GF (2^16)or GF (2^32) in a certain length range. The prototype of the reconfigurable LFSR has been implemented in Altera's EP2S60F1020C5 FPGA and its highest run clock is 100MHZ. It is proved by experiment that the reconfigurable LFSR design uses few hardware resources and its performance is stable.

A5/1 is the strong version of the encryption algorithm on GSM (Global System for Mobile communications) used in many countries. It is constructed of a combination of three LFSRs (Linear Feedback Shift Registers) with irregular clocking manner. One of the most practical attacks against this algorithm is time-memory trade-off attack, which is based on birthday paradox. The goal of this attack is to find any intersection between precomputed LFSRs states set and set of states generating the output bits in the actual execution of the algorithm. In order to increase feasibility of this attack, the biased birthday attack was introduced. In this attack special states producing a specific pattern in output bits are sampled and only a fraction of the special states with higher probability of occurrence are stored. By using a 16-bit pattern of data there are 248 parallelizable preparation stages. This attack requires about 150 GB of memory and two minutes of conversation. Under these conditions, the probability of collision is about 0.61. In this paper an improvement in the collision probability is introduced without changing the available memory capacity and duration of conversation. Our approach is based on using multiple data patterns instead of using a single one. This approach leads to increment of the preprocessing and the collision probability. It is shown that there is a trade-off between the collision probability and the preprocessing complexity.

In recent years, radio frequency identification technology has moved into the mainstream applications that help to speed up handling of manufactured goods and materials. RFID tags are divided into two classes: active and passive. Active tag requires a power source that's why its cost is more than passive tags. However, the low-cost RFID tags are facing new challenges to security and privacy. Some solutions utilize expensive cryptographic primitives such as hash or encryption functions, and some lightweight approaches have been reported to be not secure. This paper describes a lightweight Mutual authentication and ownership transfer protocol utilizing minimalistic cryptography using Physically Unclonable Functions (PUF) and Linear Feedback Shift Registers (LFSR). PUFs and LFSRs are very efficient in hardware and particularly suitable for the low-cost RFID tags. To functioning security in low cost RFID tag minimum gate requirement is 2000 gates. To implement security protocols using PUF and LFSR functions need only approx 800 gates. In this paper it is explained how we can authenticate and transfer ownership of low cost RFID tag securely using LFSR and PUF as compared to existing solutions based on hash functions.

Linear feedback shift register (LFSR) is an important component of the cyclic redundancy check (CRC) operations and BCH encoders. The contribution of this paper is two fold. First, this paper presents a mathematical proof of existence of a linear transformation to transform LFSR circuits into equivalent state space formulations. This transformation achieves a full speed-up compared to the serial architecture at the cost of an increase in hardware overhead. This method applies to all generator polynomials used in CRC operations and BCH encoders. Second, a new formulation is proposed to modify the LFSR into the form of an infinite impulse response (IIR) filter. We propose a novel high speed parallel LFSR architecture based on parallel IIR filter design, pipelining and retiming algorithms. The advantage of the proposed approach over the previous architectures is that it has both feedforward and feedback paths. We further propose to apply combined parallel and pipelining techniques to eliminate the fanout effect in long generator polynomials. The proposed scheme can be applied to any generator polynomial, i.e., any LFSR in general. The proposed parallel architecture achieves better area-time product compared to the previous designs.