An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment

This paper presents a smoothing technique for the output sequence of linear feedback shift registers (LFSR) to reduce power consumption in test-per-scan built-in self-test (BIST) applications. The proposed smoother is implemented by adding one multiplexer between the LFSR and scan-chain input of a single scan-chain. The size of the multiplexer is determined the desired smoothing degree. When the smoothed sequence of the LFSR is used to feed the test patterns in test-per-scan BIST, it reduces the number of transitions that occur at scan-chain input during scan shift operations by 25% to 50% depending on the smoothing degree, and hence reduces switching activity in the circuit-under-test (CUT) during test application. The proposed technique can be extended to multiple scan-chains BIST, also to test-per-clock applications. Various properties of the proposed technique and the methodology of the design are presented in this paper. Experimental results for the ISCAS'89 benchmark circuits show that the proposed design can reduce the switching activity up to 55% with a negligible effect on the fault coverage and test application time.

In this paper, a 4-bit Linear Feedback Shift Register (LFSR) is implemented based on a well-designed architecture combining using Pass-Transistor (PT) and Clock Complementary Metal Oxide Semiconductor (C2MOS) logic techniques. The D-flip flop registers and the XOR gates are the main parts of the propose LFSR. Number of transistors along with the speed of LFSR were positively enhanced since the exploited logic design techniques tends to blend the flavor of NMOS and PMOS devices. The PSpice and Field Programmable Gate Array (FPGA) based on Hardware Description Language (HDL) are the two different LFSR implementation environments. It has been observed that LFSR performance was effectively improved in terms of size and speed. Therefore, paper’s main aim refers to decreasing in number of transistors as well as speeding up LFSR circuit. A minimum clock time of 5ns was recorded under clearly correct LFSR output patterns. The LFSR circuit Based CMOS techniques can reduce the exploited transistors up to 43% of the conventional C2MOS logic. Besides, the number of transistors being reduced reflects the achieved circuit’s size reduction. It was concluded that paying attention to the design of the main LFSR circuit parts contributes mainly in the enhancement of the whole circuit performance.

Many Built-in Self Test (BIST) pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs of patterns for delay faults testing with LFSRs. A new synthesis procedure for a n-size LFSR is given and guarantees that a deterministic set of n precomputed test pairs is embedded in the maximal length pseudo-random test sequence of the LFSR. Sufficient and necessary conditions for the synthesis of this pseudo-deterministic LFSR are provided and show that at-speed delay faults testing becomes a reality without any additional cost for the LFSR. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other technique proposed so far.

In this paper we describe an optimized BIST scheme based on reseeding of multiple polynomial Linear Feedback Shift Registers (LFSRs). The same LFSR that is used to generate pseudo-random patterns, is loaded with seeds from which it produces vectors that cover the testcubes of difficult to test faults. The scheme is compatible with scandesign and achieves full coverage as it is based on random patterns combined with a deterministic test set. A method for processing the test s et to allow for efficient encoding by the .scheme is described. Algorithms for Calculating LFSR seeds from the test set and for the selection and ordering of polynomials are described. Experimental results are provided for ISCAS-89 benchmark circuits to demonstrate the effectiveness of the scheme. The scheme allows an excellent trade-off between test data storage and test application time (number of test patterns) with a very small hardware overhead. We show the trade-off between test data storage and number of test patterns under the scheme.

Linear feedback shift register (LFSR) is an important part of sequence cipher. In this paper, we introduce a kind of reconfigurable LFSR design. According to need, it can be configured to be a random LFSR to run over GF (2), GF (2^8) ,GF (2^16)or GF (2^32) in a certain length range. The prototype of the reconfigurable LFSR has been implemented in Altera's EP2S60F1020C5 FPGA and its highest run clock is 100MHZ. It is proved by experiment that the reconfigurable LFSR design uses few hardware resources and its performance is stable.

The authors describe the design of an LSSD-(level-sensitive-scan-design) based LFSR (linear feedback shift register) which is capable of changing seeds by applying a pair of clock pulses at the time of the change. This LFSR is controlled by two separate clocks, one for the normal LFSR operation and one for the change-of-seeds option. The newly generated seeds are uniformly distributed over the entire pattern space. The change of seeds is fast, since it is accomplished by a pair of clock pulses rather than by long scan operations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In recent years, radio frequency identification technology has moved into the mainstream applications that help to speed up handling of manufactured goods and materials. RFID tags are divided into two classes: active and passive. Active tag requires a power source that's why its cost is more than passive tags. However, the low-cost RFID tags are facing new challenges to security and privacy. Some solutions utilize expensive cryptographic primitives such as hash or encryption functions, and some lightweight approaches have been reported to be not secure. This paper describes a lightweight Mutual authentication and ownership transfer protocol utilizing minimalistic cryptography using Physically Unclonable Functions (PUF) and Linear Feedback Shift Registers (LFSR). PUFs and LFSRs are very efficient in hardware and particularly suitable for the low-cost RFID tags. To functioning security in low cost RFID tag minimum gate requirement is 2000 gates. To implement security protocols using PUF and LFSR functions need only approx 800 gates. In this paper it is explained how we can authenticate and transfer ownership of low cost RFID tag securely using LFSR and PUF as compared to existing solutions based on hash functions.

Linear feedback shift register (LFSR) is an important component of the cyclic redundancy check (CRC) operations and BCH encoders. The contribution of this paper is two fold. First, this paper presents a mathematical proof of existence of a linear transformation to transform LFSR circuits into equivalent state space formulations. This transformation achieves a full speed-up compared to the serial architecture at the cost of an increase in hardware overhead. This method applies to all generator polynomials used in CRC operations and BCH encoders. Second, a new formulation is proposed to modify the LFSR into the form of an infinite impulse response (IIR) filter. We propose a novel high speed parallel LFSR architecture based on parallel IIR filter design, pipelining and retiming algorithms. The advantage of the proposed approach over the previous architectures is that it has both feedforward and feedback paths. We further propose to apply combined parallel and pipelining techniques to eliminate the fanout effect in long generator polynomials. The proposed scheme can be applied to any generator polynomial, i.e., any LFSR in general. The proposed parallel architecture achieves better area-time product compared to the previous designs.

Four Dimensional (4D) Playfair cipher fused with Linear Feedback Shift Register (LFSR) has the capability of providing confidentiality to any type of data. The main aim of this research is to compare this cipher with the standard ciphers AES-256 and RSA-2048. The comparisons are done on the basis of encryption and decryption times, plain data size versus cipher data size, possible number of keys and types of data supported. It is found from the comparison analysis that the AES-256 is efficient in terms of time, memory and bandwidth consumption when compared to the other two ciphers. For AES-256, data size has to be a multiple of 16 bytes or padded values shouldn’t be a part of original data values in order to be unambiguous while the other two ciphers are always unambiguous. Also, AES-256 is weak against brute force attack when compared to other two ciphers. Among RSA-2048 and 4D Playfair cipher fused with LFSR, latter is highly efficient in terms of time, memory and bandwidth. Therefore, applications wanting to secure all sorts of data efficiently and unambiguously irrespective of data size can use 4D Playfair cipher fused with LFSR. Keywords: Data security; Cryptography; AES; RSA; 4D Playfair cipher

Communication security that depends on chaos can be considered as a new approach which provides protection and security of communications and maintains confidentiality because Chaos theory can be implemented in cryptosystem successfully. A stream cipher, on the other hand, is a type of symmetric cryptosystem in which the plaintext is divided into small entities known as characters. The key in stream cipher is typically generated by a random bit generator. Many key stream generators employ linear feedback shift registers (LFSRs). LFSR systems are made up of a group of LFSR units and a combining function (CF) unit. The plaintext is encrypted one bit at a time. The key is fed into a random bit generator, which produces a long series of binary signals. This "key-stream" k is then combined with plaintext m, typically via a bit-wise XOR (Exclusive-OR modulo 2 addition), to produce the ciphertext stream, which employs the same random bit generator and seed. In this paper we will introduce a new stream cipher keygenerator which using a hybrid between chaotic and combination of Linear Feedback Shift Registers (LFSR's). The proposed generator can be used to protect different types of data files (text, image, audio and video). Many kinds of tests are applied to specifying the goodness of the proposed keygenerator. The results of testing prove the efficiency of the suggested system.

stream ciphers encrypt the data bit by bit. In this research a new model of stream cipher SNOW 2.0 has been proposed i.e. Non linear modified SNOW 2.0 using one Linear Feedback Shift Register (LFSR) with the embedding of non linear function in the model. The analysis of Guess and Determined (GD) attack has been done to check its security with respect to previous versions. The proposed model contains one Linear Feedback Shift Register (LFSR) along with the non linear function which increases the strength of the stream cipher, to make the static nature of modified SNOW 2.0 dynamic. The Experimental analysis show that such a mechanism has been built which provides more security than the previous version of modified SNOW 2.0 in which non linearity was either not introduced or it was introduced using two Linear Feedback Shift Registers (LFSRs). It is concluded that this version is more powerful with respect to the security of plain text against Guess and Determined attack (GD) as compared to the previous versions.

Applying Cuckoo Search for analysis of LFSR based cryptosystem

Random number generator (RNG) is a fundamental element in modern cryptography. If the quality of the outputs generated by RNGs is not as well as expected, the cryptographic applications which use the random number service are vulnerable to security threats. In reality, the entropy source of RNGs could be impressible by the changes of environmental factors, resulting in defects in the generated data, such as poor statistical properties. Thus, RNG is generally designed with a preset post-processing module to improve the quality of the output sequences. Linear feedback shift register (LFSR) is one of the frequently used methods for post-processing thanks to the characteristic of simplicity and no reduction in output throughput. However, we point out that even if the statistical properties of the outputs of the entropy source are extremely poor, the sequences processed by LFSR can still pass the statistical test. This undoubtedly increases the security risks in the usage of RNGs. In this work, we propose a distinguisher for the RNGs with LFSR post-processing for the first time. The distinguisher can be used to detect the RNGs with LFSR post processing, and we theoretically prove the sequences before processing can be recovered. On this basis, we design a new statistical test via combining the distinguisher with the Frequency Test in the NIST test suite. The experimental results show that if the sequence is biased before being processed by LFSR, our proposed method can detect it, but the NIST SP 800-22 Test Suite cannot.KeywordsRandom number generatorLFSRPost-processingDistinguisherRandomness test

We propose a sequential test pattern decompressor enabling dynamic reseeding. It reduces dependency between the decompressor output bits during the first few clock cycles after decompressor reset. Due to this fact, a lower number of clock cycles is necessary to be performed in order to encode test patterns. We evaluated features influencing the decompression quality and the hardware overhead for different decompressor principles. According to the evaluation results, we propose a decompressor combining a combinational linear decompressor and an linear feedback shift register (LFSR) like automaton, we place the combinational decompressor on the LFSR inputs. We demonstrate that due to this arrangement the combined decompressor can be used without any phase shifter and/or state skipping ability of the LFSR. We have experimentally verified that adopting the proposed decompressor structure improves test coverage, saves the hardware resources and shortens the test application time.

The main challenging areas in VLSI design are performance, cost, testing, area, reliability and power. The demand for portable computing devices and communication system are increasing rapidly. The power dissipation during test mode is much more than in normal mode. Hence it is important to optimize power during testing. BIST is a Design for Testability (DFT) technique, because it makes the electrical testing of a chip easier, faster, more efficient, and less costly. Hence the low power Multiple Single Input Change (MSIC) test patterns are generated for BIST based schemes. The characteristics of these multiple single input change patterns are minimum transition, uniform distribution and uniqueness of patterns. A reconfigurable Johnson counter, XOR array and a seed generator are used for generating test patterns. The seed generator is a linear feedback shift register. A single seed or multiple seeds can be used which will affect the number of patterns generated. Since the patterns are of low transitions, the power dissipation during test mode can be reduced. Here the generated patterns are given to different scan chains. To reduce the hardware overhead, delay and power consumption an accumulator based circuit can be used. The generated patterns are applied to the s344 benchmark circuit for fault injection and fault detection. The coding is done in VHDL and is simulated in XILINX ISE simulator.