Analysis of Low Power High Speed Parallel Prefix Adder Using Cadence Encounter Platform

The field of cryptography has seen remarkable progress with the introduction of three operand binary adders in the applications of pseudo-random bit generators (PRBG). This is especially true in the case of Modified dual-CLCG (MDCLCG) being it the safest and most random PRBG method. Parallel prefix adders which are extensively used for fast binary addition can be extended towards the use in three operand binary adders hence making them much more efficient. In this paper, all the basic six topologies of Parallel Prefix Adders – Han Carlson, Kogg – Stone, Brent – Kung, Sklansky, Ladner - Fischer and Knowles adders are used within the four stage architecture of a multi - bit three operand adder. All the adder designs with the word sizes of 16, 32 and 64-bit have been simulated and implemented on Xilinx Vivado Design Suite 2020.2 using the programming language Verilog HDL The architecture of these three operand adders are prototyped on the commercially available Basys 3 Artix-7 FPGA Board for the on-chip functional verification. Further, all these designs are synthesized using Cadence tool with GPDK 45nm technology library for the purpose of comparing various adders with respect to performance parameters – area, delay and power for the different word sizes.

An Efficient Implementation of Hybrid Carry Select Adder Using Parallel Prefix Addition and Binary to Excess 1 Conversion

This paper presents a comparative study of delay, power consumption, area efficiency, and a review of six different architectures of adders, namely Brent-Kung, Ladner-Fischer, Han-Carlson, Kogge-Stone, Sklansky, and Sparse Kogge Stone Adder. An adder is one of the basic building blocks of a digital circuit, which is used in a wide range of arithmetic calculations in microprocessors, ALUs, and signal controllers. Adders play a critical role in the digital computing environment where addition, subtraction, and multiplication must be performed as efficiently as possible. Parallel prefix adders are an example of how modern adders like Brent-Kung and Ladner-Fischer work. The study derives thorough simulations and analyses through Cadence Virtuoso, which analyzes the delay, power consumption, and transistor population of each adder to showcase their merits and demerits. The study is confined within the scope of design simulation and measurement of performance on the different architectures of the adders based on 45 nm technology, which aims to provide a complete analysis for choosing the most appropriate designs for effective high-speed digital systems.

Objective: The Ultimate aim of the VLSI Design is to improve the efficiency, Reduction of Delay and Power Consumption and to minimize the area. In our proposed approach we had implemented the analysis had been done on the field of Speed, Power consumption, Area and Power delay product (PDP) for a carry skip adder with other adders listed as the parallel prefix adders and others. Methods/Statistical Analysis: The Carry-Skip Adder planned here reduces the time required to propagate the carry by skipping over teams of consecutive adder stages, is understood to be comparable in speed to the carry look-ahead technique whereas it uses less logic space and fewer power. Findings: The adders are basic building blocks of the digital circuits for the Signal processing, Integrating and other process of operation. There are various types of adders are proposed in Literature which are commonly used in VLSI Design. The Simulation results also shows that the proposed adder Architecture is Faster and Area efficient compared to other existing adder architecture. Application/ Improvements: They estimate the performance of proposed design will be better in terms of Logic and route delay by experimental results. Keywords: Adders, Carry Bypass Adder (CBA), Carry Increment Adder (CIA), Carry Look-Ahead Adder (CLA), Carry Skip Adder (CSkA), Han Carlson Adder (HCA), Ripple Carry Adder (RCA)

Multipliers play a important role in current signal processing chips like DSP and general purpose processors and applications. In such high performance systems addition and multiplication operations are fundamental and most used arithmetic operations. Some case study shows that more than 70% of DSP algorithms and in microprocessor operations perform addition and multiplication. Hence these operations dominate the execution time. To meet the processing speed demand, the design of multipliers and adders plays a vital role. Low power consumption has consumption has became a major issue in design of multiplier. To reduce the power consumption, the components used in the design must be drastically reduced and in parallel it should not degrade the other performance metric. In this paper we are proposing a new architecture to design multiplier using parallel prefix adders. The Parallel Prefix Adder (PPA) have fast carry generation network and hence they are the fastest types of adder that had been created and developed. Most common types of parallel prefix adder are Brent Kung and Kogge Stone adders. The performances of these two adders in terms of worst case delay and transistor count and power consumption studied and an analysis of the same is presented. Utilizing the same to design and implement the multiplier using PPA is performed in this paper.

This paper evaluates the performance of the gate diffusion input technique (GDI) on self-checking and self-resetting logic (SRL) GDI technique of carry select adder (CSA) and carry look-ahead adder (CLA) for different word lengths. In the proposed design adapting level restoration technique eliminates conductance overlap between n-MOS and p-MOS devices. The various self-resetting logic implementations for self-correcting of carry select adder and carry look-ahead adder can detect all single stuck faults in normal operation mode. Besides, two rail encoding technique is used in carry select adder are used for multiple error detection/correction. The SRLGDI setup consists of a pair of full adders, multiplexers, two rail checking, and self-resetting logic. In this technique, the self-checking carry select adder is used for reducing area and self-resetting improves the performance of the adder. The analysis of CSA and CLA with 180nm technology is simulated by using Cadence tools. The delay reduction is 12.836% for 8-bit CLA using SRL GDI, power reduction is 27.55% for 8-bit CSA using SRL-GDI compared to the gate diffusion input technique. This GDI technique implementation saves the average energy consumption up to 31.14% in CSA and 32.83% in CLA making it suitable for power optimization in high speed VLSI systems.

In this paper, a power efficient gain boosting current mirror with fast stand-by recovery (4.5μs) and a maximum gain of 80dB is proposed in a 0.35μm CMOS process with 3V power supply. The gain is achieved from the aspect ratios in transistors and deployed closed loop amplifier. In active mode, it can deliver upto 1mA from 0.1μA input current with approximately 1.2μA in biasing circuits. It consumes only 0.8μW during stand-by mode. A digital calibration circuit is employed to overcome device mismatch and process variation. This generates accurate output currents within a range of ±8%, whereas without calibration, the variation of ±33% at output currents is observed. This technique can be used in biomedical devices, which seek high power efficiency.

High-speed multiplication is a fundamental requirement in modern computing systems, including applications in digital signal processing (DSP), artificial intelligence (AI), and cryptography. This paper presents an optimized 64-bit Dadda multiplier incorporating a Brent-Kung Adder (BKA) and 4:2 compressors to enhance speed and efficiency. The Dadda multiplier is widely recognized for its reduced number of reduction stages, significantly minimizing delay and hardware complexity. The integration of the Brent-Kung Adder, a parallel prefix adder with logarithmic delay, further improves performance by reducing carry propagation delay in the final addition stage. The proposed design is implemented in Verilog and synthesized on an FPGA to evaluate its efficiency in terms of delay, power consumption, and area utilization. A comparative analysis is conducted against 32-bit Dadda multipliers utilizing Ripple Carry Adder (RCA) and Carry Select Adder (CSLA), demonstrating that the 64-bit Dadda multiplier with BKA achieves superior speed while maintaining reasonable power and area efficiency. Simulation results reveal that the proposed design achieves a propagation delay of 28.228 ns, significantly lower than traditional approaches. The inclusion of 4:2 compressors further optimizes partial product reduction, ensuring a more efficient multiplication process. By leveraging an optimized reduction strategy and an efficient parallel prefix adder, this work provides a robust solution for real-time applications requiring high-speed arithmetic computations. The balance between speed, power, and hardware utilization makes this design a practical choice for applications demanding efficient multiplication operations.

This paper addresses design strategies and tradeoffs of a series of newly developed interleaving switched-capacitor power converters. In such a design, a converter consists of multiple sub-cells in the power stage, and is regulated with interleaving power flow control. By splitting the power flow in a time-sequenced manner, the converter maintains a continuous power delivery flow to the output V OUT, with significant reductions on the in-rush input current and the output voltage ripples. System modeling and optimization focusing on power efficiency and z-domain closed-loop gain enhancement are discussed. An experimental prototype was successfully fabricated with a standard 0.35-μm digital CMOS N-well process. The entire die area, including fully integrated pads and power devices, is 3.84 mm2. Measurement results show that, with a supply voltage of 1.5 V and a load of 250 mA, the output of the converter is well regulated at 2.5 V with 16-mV ripple. The maximum efficiency of 82.3% is achieved at the output power of 625 mW.

GeTe Thermoelectrics

High-performance single-threaded processors achieve their performance goal partly by relying, among other architectural techniques, on speculation and large on-chip caches. The hardware to support these techniques is usually a large portion of the overall processor real state area, and therefore it consumes a significant amount of power that sometimes is not optimally used toward doing useful work. In this work, we study the intuitive fact that architectures with hardware support for threads are more power efficient than a more traditional single-threaded superscalar architecture. Toward this goal, we have created a model of the power, performance and area of several parallel architectures. This model shows that a parallel architecture can be designed so that (a) it requires less area and power (to reach the same performance), or (b) it achieves better power efficiency and less area (for the same power budget), or (c) it has higher performance and better power efficiency (for the same area constraint), when compared to a single-threaded superscalar architecture.

New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementations is available to deliver computation with varying degrees of area and power efficiency, from general-purpose processors to application-specific integrated circuits (ASICs). The tradeoff of moving towards more efficient customized solutions such as ASICs is the lack of flexibility in terms of hardware reusability and programmability. In this paper, we propose a customized semi-programmable loop accelerator architecture that exploits the efficiency gains available through high levels of customization, while maintaining sufficient flexibility to execute multiple similar loops. A customized instance of the loop accelerator architecture is generated for a particular loop and then the data and control paths are proactively generalized in an efficient manner to increase flexibility. A compiler mapping phase is then able to map other loops onto the same hardware. The efficiency of the programmable accelerator is compared with non-programmable accelerators and with the OpenRISC 1200 general purpose processor. The programmable accelerator is able to achieve up to 34x better power efficiency and 30x better area efficiency than a simple general purpose processor, while trading off as little as 2x power and area efficiency to the non-programmable accelerator.

The complexity of current Deep learning has been growing rapidly nowadays. Such advancement allows various organizations such as private sectors and government to leverage intelligent systems on their use cases. High Performance Computing (HPC) infrastructure nowadays has pivoted to GPU-oriented systems, enabling developers and researchers to train complex models with large datasets unlike conventional clusters equipped only with CPU cores. However, focus on power efficiency on the HPC system has not been prevalent especially on the new system such as DGX A100 that does not have datapoints on how GPUs consumed power. Even though such HPC cluster can be powerful, always allowing it to run at the maximum capacity results to financial cost to the HPC provider at the end. Therefore, for any organization providing the system, it is crucial for them to balance the cluster capabilities while maintaining overall power consumption which can potentially be costly in the long term. This paper reveals A100 GPU metrics that are relevant to Power usage and explains GPU profiling applied to Deep learning workload on the cluster, saving up to 32% of the power usage while compromising only 11.5% of training time compared to a default profile. Then, the paper investigates literature review that could be learned further adopted to the current system at CMKL university as the next milestone.

SummaryThe emergence of power efficiency as a primary constraint in processor and system design poses new challenges concerning power and energy awareness for numerical libraries and scientific applications. Power consumption also plays a major role in the design of data centers, which may house petascale or exascale‐level computing systems. At these extreme scales, understanding and improving the energy efficiency of numerical libraries and their related applications becomes a crucial part of the successful implementation and operation of the computing system. In this paper, we study and investigate the practice of controlling a compute system's power usage, and we explore how different power caps affect the performance of numerical algorithms with different computational intensities. Further, we determine the impact, in terms of performance and energy usage, that these caps have on a system running scientific applications. This analysis will enable us to characterize the types of algorithms that benefit most from these power management schemes. Our experiments are performed using a set of representative kernels and several popular scientific benchmarks. We quantify a number of power and performance measurements and draw observations and conclusions that can be viewed as a roadmap to achieving energy efficiency in the design and execution of scientific algorithms.

Addition is a timing critical operation in today's floating point units. In order to develop faster processing, an end-around carry (EAC) was proposed as a part of fused-multiply-add unit which performs multiplication followed by addition [5]. The proposed EAC adder was also investigated through other prefix adders in FPGA technology as a complete adder [6]. In this thesis, we propose a 128-bit standalone adder with parallel prefix end around carry logic and conditional sum blocks to improve the critical path delay and provide flexibility to design with different adder architectures. In previous works, CLA logic was used for EAC logic. Using a modified structure of a parallel prefix 2n-1 adder provides flexibility to the design and decreases the length of the carry path. After the architecture is tested and verified, critical path is analyzed using FreePDK45nm library. Full custom design techniques are applied carefully during critical path optimization. Critical path analysis provides fast comparison of the total delay among different architectures without designing the whole circuit and a simpler approach to size the transistors for lowest delay possible. As a final step, datapath is designed as a recurring bitslice for fast layout entry. The results show that the proposed adder shows 142ps delay, 2.42mW average power dissipation, and 3,132 sq. micron area assuming there is not much routing area overhead in the estimated area.