Design Space Exploration of High-Performance Parallel Architectures

New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementations is available to deliver computation with varying degrees of area and power efficiency, from general-purpose processors to application-specific integrated circuits (ASICs). The tradeoff of moving towards more efficient customized solutions such as ASICs is the lack of flexibility in terms of hardware reusability and programmability. In this paper, we propose a customized semi-programmable loop accelerator architecture that exploits the efficiency gains available through high levels of customization, while maintaining sufficient flexibility to execute multiple similar loops. A customized instance of the loop accelerator architecture is generated for a particular loop and then the data and control paths are proactively generalized in an efficient manner to increase flexibility. A compiler mapping phase is then able to map other loops onto the same hardware. The efficiency of the programmable accelerator is compared with non-programmable accelerators and with the OpenRISC 1200 general purpose processor. The programmable accelerator is able to achieve up to 34x better power efficiency and 30x better area efficiency than a simple general purpose processor, while trading off as little as 2x power and area efficiency to the non-programmable accelerator.

Solid state disks (SSDs) consisting of NAND flash memory are replacing conventional HDDs in mobile and server markets. The major reason for such a widespread replacement is the high performance and low power consumption enabled by an SSD. It especially gives better performance and power efficiency for random requests, because it does not require slow-moving and power-hungry mechanical operations, e.g., motor control. For the performance of sequential requests, multi-channel/way parallel architectures are adopted, and the speed of the host interface is increased. Even though an SSD has better power efficiency than an HDD, the SSD power consumption must be minimized due to the stringent power consumption constraints of mobile and server products. This chapter presents a case study of developing an SSD power model with an application to low power SSD design. The power model is based on real measurement data. For accurate modeling, one must take into account the internal parallelism as well as power states. The case study shows that the power model is useful in evaluating the designs of dynamic power management policy.

Modern high performance Chip Multiprocessor (CMP) systems rely on large on-chip cache hierarchy. As technology scales down, the leakage power of present SRAM based cache gradually dominates the on-chip power consumption, which can severely jeopardize system performance. The emerging nonvolatile Spin Transfer Torque RAM (STT-RAM) is a promising candidate for large on-chip cache because of the ultra low leakage power. However, the write operations on STT-RAM suffer from considerably higher energy as well as longer latency compared with SRAM which will make STT-RAM in trouble for write-intensive workloads. In this paper, we propose to integrate SRAM with STT-RAM to construct a novel hybrid cache architecture for CMPs. We also propose dedicated microarchitectural mechanisms to make the hybrid cache robust to workloads with different write patterns. Extensive simulation results demonstrate that the proposed hybrid scheme is adaptive to variations of workloads. Overall power consumption is reduced by 37.1% and performance is improved by 23.6% on average compared with SRAM based static NUCA under the same area configuration.

Processing-in-memory (PIM) is rapidly rising as a viable solution for the memory wall crisis, rebounding from its unsuccessful attempts in 1990s due to practicality concerns, which are alleviated with recent advances in 3D stacking technologies. However, it is still challenging to integrate the PIM architectures with existing systems in a seamless manner due to two common characteristics: unconventional programming models for in-memory computation units and lack of ability to utilize large on-chip caches. In this paper, we propose a new PIM architecture that (1) does not change the existing sequential programming models and (2) automatically decides whether to execute PIM operations in memory or processors depending on the locality of data. The key idea is to implement simple in-memory computation using compute-capable memory commands and use specialized instructions, which we call PIM-enabled instructions, to invoke in-memory computation. This allows PIM operations to be interoperable with existing programming models, cache coherence protocols, and virtual memory mechanisms with no modification. In addition, we introduce a simple hardware structure that monitors the locality of data accessed by a PIM-enabled instruction at runtime to adaptively execute the instruction at the host processor (instead of in memory) when the instruction can benefit from large on-chip caches. Consequently, our architecture provides the illusion that PIM operations are executed as if they were host processor instructions. We provide a case study of how ten emerging data-intensive workloads can benefit from our new PIM abstraction and its hardware implementation. Evaluations show that our architecture significantly improves system performance and, more importantly, combines the best parts of conventional and PIM architectures by adapting to data locality of applications.

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A DSP/FPGA-based parallel architecture oriented to real-time image processing applications is presented. The architecture is structured with high performance DSPs interconnected by FPGA. Within FPGA a FIFO interconnection network and the specific data communication protocol are implemented, which interconnect 3 DSPs (TMS320C6414) effectively. The measured performances in the prototype with the proposed parallel architecture, including inter-DSP data communication performance and system computing capacity, show high data transfer bandwidth (up to 400 Mbytes/s) with low latency as well as high image processing performance, which achieve a good balance for parallel image processing.

In this paper we focus on MPSoC architectures for human heart ECG real-time monitoring and analysis. This is a very relevant bio-medical application, with a huge potential market, hence it is an ideal target for an application-specific SoC implementation. We investigate a symmetric multi-processor architecture based on STMicroelectronics VLIW DSPs that process in real-time 12-lead ECG signals. This architecture improves upon state-of-the-art SoC designs for ECG analysis in its ability to analyze the full 12 leads in real-time, even with high sampling frequencies, and ability to detect heart malfunction. We explore the design space by considering a number of hardware and software architectural options.

The rapid advancement of programmable logic devices (PLDs) and field-programmable gate arrays (FPGAs) has enabled the development of adaptive VLSI architectures optimized for next-generation wireless communication systems. This research focuses on RFID and Wireless Sensor Network (WSN) applications, integrating AI-driven optimization techniques to enhance power efficiency, processing speed, and system adaptability. A hybrid AI-based hardware optimization technique, combining Reinforcement Learning (RL) and Genetic Algorithm (GA), is introduced to improve resource utilization and reduce latency. Additionally, an AI-Optimized Dynamic Frequency Scaling (DFS) technique is implemented to adjust FPGA operating frequencies in real-time, achieving a power reduction of 27.6% while maintaining high computational efficiency. Processor implementation for RFID-based power-saving appliances, reducing power consumption by 32.5% compared to conventional approaches. Hardware realization of an optimized anti-collision algorithm for RFID, achieving a 24.8% increase in tag identification speed. FPGA-based security architecture integrating lightweight cryptographic techniques, enhancing data security with a 96.2% encryption success rate and 25% lower hard-ware resource usage. Power-efficient WSN node implementation using an adaptive localization algorithm, reducing localization errors by 18.4% and extending node lifespan by 29.3%. Low-power CORDIC algorithm-based DPSK modem implementation with 32.1% lower latency in real-time signal processing applications. AI-Optimized DFS technique, reducing dynamic power consumption by 27.6% and improving computational throughput by 22.7%, making FPGA implementations more energy-efficient. The designs were developed using VHDL-based high-level hardware description, simulated in Xilinx ISE 14.3, and implemented on Virtex-5, Spartan-6, and Kintex-7 FPGA platforms. Performance evaluations and comparative studies with existing models confirm significant improvements in power efficiency, processing speed, and adaptability. The findings contribute to the development of high-performance, power-efficient, and scalable VLSI architectures for RFID and WSN applications, paving the way for next-generation secure and intelligent wireless communication systems.

I. ABSTRACT High performance in the age of lightning-fast computing and energy-efficient electrical devices depends on the creation of optimised arithmetic units. The efficiency of adders, which are crucial components of the majority of digital systems, has a direct effect on the system's overall speed and power usage. In this study, a low-power, high-speed parallel prefix adder (PPA) architecture leveraging Cadence nclaunch is designed and implemented. In terms of gates, power, and area, prefixes topologies such as Brent-Kung and Kogge-Stone are examined and contrasted. The suggested architecture uses effective gate-level implementations and logic-level optimisations to lower power consumption without sacrificing speed. To confirm functionality and performance, the design is synthesised and simulated using the cadence tool. When compared to traditional adder architectures, the findings show a notable gain in both power efficiency and area, demonstrating the usefulness of the suggested integration strategy in contemporary low-power, high-speed VLSI systems. Keywords: PPA, EDP, SoC, FPGA.

According to recent research, with the ever-increasing use of Internet of Things (IoT) devices, there has arisen an ever-growing need for high-performance yet low-power circuits that can efficiently process information. Quantum-dot Cellular Automata (QCA) has emerged as a promising alternative to conventional complementary metal-oxide-semiconductor (CMOS) technology due to its great potential in digital design at nanoscale levels on account of very low power consumption and very high processing speed. However, QCA circuits are inherently prone to faults due to variations in manufacturing processes and due to the influence of environmental factors. These faults degrade the performance of a QCA circuit considerably. Hence, fault tolerance is one of the major factors of consideration while designing a QCA circuit, particularly when the application requires very reliable and continuous operation, say in an IoT system. As such, this work presents a fault tolerant Carry Skip Adder (CSA) for QCA-based circuits. The fault tolerance of basic arithmetic components of IoT nodes performing tasks corresponding to the signal processing, control, and data manipulations is enhanced in the proposed architecture. The area occupied by a fault-tolerant full-adder circuit is 0.06 μm² and a clock cycle is 0.75; its core will be used in the CSA design. It realizes fault-tolerant multiplexers (MUX) and a majority gate, which gives the same result when there is a missing or extra single-cell fault. The most astonishing characteristic of this transistor-based CSA is its 85% tolerance for different types of failures. The CSA with three layers contains 1542 quantum cells, 4.75 clock phases, and occupies an area of 4.59 μm². It is compact and efficient architecture; therefore, it is very suitable for IoT applications where the area constraint and power efficiency are the key issues. The proposed CSA will increase the robustness and reliability of QCA-based digital circuits by integrating fault tolerance into its design such that the circuitry based on QCA can keep their functionality on even in fault-prone environments.

In this paper a tool aimed at generating fast Fourier transform (FFT) cores targeting FPGA platforms was presented. The tool is able to generate different pipelined architectures of the FFT that provide different points of the design space: from high performance to low area implementations. The user can select the most suitable architecture based on a broad set of configuration parameters, as they are the number of points, sample size, truncation, etc. Moreover, a set of accurate estimators has been implemented to allow the designer an early and quick design space exploration before synthesizing the core. Experimental results validate our approach and provide significant measurements about the accuracy of the estimation and the tool execution time

Our recently proposed distributed module cluster (DMC) micro-architecture, which is used for long-bit modular multipliers of RSA cryptosystems, is based on a systolic array in which the processing cells are all one-bit long. In the design space exploration of this DMC architecture with TSMC deep sub-micron CMOS standard-cell technology, various widths of processing cells are implemented in the systolic array. The result analysis shows that when the fully serial systolic architecture is used, in which one cell processes one bit, the DMC architecture achieves the highest frequency hence the best performance. If the time and area overhead is represented as time-area product, it is one of the most cost-efficient designs as well

Homogeneous multicore processors such as the ones proposed by Intel or AMD have become mainstream. However heterogeneous architectures, such as multicore associated with GPUs or with any hardware specialized co-processors usually offer a much higher peak performance/power ratio. When high performance and power efficiency has to be achieved, specialized hardware is often the way to go. Combining a general-purpose multicore with a highly parallel coprocessor, e.g., GPU, allows to both achieve high speedups on parallel sections while maintaining high performance on control sections. However, programming such heterogeneous architectures is quite a challenge for any application developer. The embedded market has been living with it for decades but at a very high programming cost. The general-purpose computing is now entering this era. Manycore performance opens HPC to many new scientific and consumer applications. New multimedia, medical and scientific applications will be developed by hundreds of thousands of engineers across the world. These applications, usually provided by ISV, will have to be tuned for thousands of various platform configurations built with different hardware units such as CPUs, GPUs, accelerators, PCIx buses, memories, etc., each configuration having its own performance profile. Furthermore, in most manycore systems, applications are in competition at run-time for hardware resources like the memory space of accelerators. If ignored this can lead to a global performance slowdown. The past of parallel programming is scattered with hundreds of parallel languages, most of them were designed to address homogeneous architectures and concerned a small and well-trained community of HPC programmers. With the new diversity of parallel hardware platforms and the new community of non-expert developers, expressing parallelism is not sufficient anymore. Resources management, application deployment, and portable performance are interconnected issues that require to be addressed holistically. As many decisions should be taken according to the available hardware, resources management cannot be moved apart from parallel programming. Deploying applications on various systems without having to deal with thousands of configurations is the main concern of ISVs. The grail of parallel computing is to be able to provide portable performance by making hardware changes transparent for a large set of machines and fluctuating execution contexts. Are general-purpose compilers obsolete? Compilers are keystone solutions of any approaches that deal with previous challenges. But general-purpose compilers try to embrace so many domains and try to serve so many constraints that they frequently fail to achieve very high performance. They need to be deeply revisited! Recent techniques are showing promises. Iterative compilation techniques, exploiting the large CPU cycle count now available on every PC, can be used to explore the optimization space at compile-time. Second, machine-learning techniques, e.g. Milepost project ( http://www.milepost.eu/ ), can be used to automatically improve code generation compilers strategies. Speculation can be used to deal with necessary but missing information at compile-time. Finally, dynamic techniques can select or generate at run-time the most efficient code adapted to the execution context and available hardware resources. Future compilers will benefit from past research, but they will also need to combine static and dynamic techniques. Moreover, domain specific approaches might be needed to ensure success. Biography of Francois Bodin Francois Bodin cofounded CAPS (www.caps-entreprise.com) in 2002 while he was a Professor at University of Rennes I and since January 2008 he joined the company as CTO. His contribution includes new approaches for exploiting high performance processors in scientific computing and in embedded applications. Prior to joining CAPS, Francois Bodin held various research positions at University of Rennes I and at the INRIA research lab. He has published over 60 papers in international journals and conferences and he has supervised over 15 PhD thesis. Professor Francois Bodin holds a Master's in CS and a PhD in CS, both from University of Rennes I.

This paper presents an analytical comparison between the Automatic Packet Reporting System (APRS) and LoRaWAN protocols, focusing on their applicability in nanosatellite telemetry, emergency communication, and remote sensing networks. Based on a structured review of 14 verified scientific sources published between 2019 and 2024, the study evaluates both protocols across ten key technical parameters, including data rate, power efficiency, link budget, security, error resilience, and integration within satellite stacks. The analysis adopts a matrix-based comparative methodology, drawing on normalized and cross-referenced empirical data extracted from real-world deployments. APRS is identified as a resilient, infrastructure-independent protocol suitable for minimalist and disaster-prone missions, especially where decentralization and simplicity are required. In contrast, LoRaWAN demonstrates superior throughput, AES-128 encryption, and flexible scalability, making it a strong candidate for next-generation low-power satellite IoT architectures. The paper emphasizes the scarcity of side-by-side protocol evaluations in current literature and highlights the need for unified assessment criteria. It proposes hybrid mission models where LoRaWAN functions as the primary communication layer and APRS serves as a redundant backup channel. This work contributes a structured reference framework to support system designers, researchers, and mission planners in selecting or integrating these technologies for power-constrained telemetry applications in space and terrestrial domains.