Analysis of MTJ based STT-MRAMs cell modeling and design perspective

Integration and co-design of CMOS and spin transfer devices requires accurate vector spin conduction modeling of magnetic tunnel junction (MTJ) devices. A physically realistic model of the MTJ should comprehend the spin torque dynamics of nanomagnet interacting with an injected vector spin current and the voltage dependent spin torque. Vector spin modeling allows for calculation of 3 component spin currents and potentials along with the charge currents/potentials in non-collinear magnetic systems. Here, we show 4-component vector spin conduction modeling of magnetic tunnel junction devices coupled with spin transfer torque in the nanomagnet. Nanomagnet dynamics, voltage dependent spin transport, and thermal noise are comprehended in a self-consistent fashion. We show comparison of the model with experimental magnetoresistance (MR) of MTJs and voltage degradation of MR with voltage. Proposed model enables MTJ circuit design that comprehends voltage dependent spin torque effects, switching error rates, spin degradation, and back hopping effects.

In this paper, the authors propose a non-volatile flip-flop, which presents simultaneously low power dissipation and high speed. This flip-flop is based on MRAM (magnetic RAM) technology on standard CMOS. In this non-volatile flip-flop design, the authors use magnetic tunnel junctions (MTJ) as storage element. Contrary to the complex sense amplifier circuit in standard MRAM circuits, a simple one based on SRAM cell is used to couple with two MTJs per bit in magnetic logic circuit. The flip-flop works exactly as a classical flip-flop hut the information is stored simultaneously in the two MTJs, which makes this flip-flop non-volatile. As the writing frequency has a strong impact on the power consumption, the MTJ writing frequency is designed to be defined by the users depending on different usage. During the startup or reset phase, the flip-flop master stage is used as the MTJ sense amplifier and the flip-flop is initialized to the previously stored state in about 200 ps. This figure has been demonstrated by electrical simulation on a 90 nm CMOS technology and with a complete and precise MTJ model

Effect of magnetic coupling between two CoFeB layers on thermal stability in perpendicular magnetic tunnel junctions with MgO/CoFeB/insertion layer/CoFeB/MgO free layer

Spin-transfer torque random access memory (STT-RAM) is a promising candidate for universal memory due to its speed, scalability, and non-volatility. A wide range of write speeds from 1 to 100 ns have been reported for STT-RAM. As the storage element of an STT-RAM cell, the switching current of magnetic tunnel junction (MTJ) is inversely proportional to the write pulse width. In this work, we propose a methodology to design STT-RAM for different optimization goals such as read performance, write performance, and write energy by leveraging the trade-off between write current and write time of MTJ. To enable STT-RAM design in advanced technology nodes beyond 22 nm, we model perpendicular MTJ (PMTJ) as the storage element and FinFET as the access transistor. Our study shows that reducing write pulse width will harm read latency and energy. It is observed that "sweet spots" of write pulse width which minimize the write energy or write latency of an STT-RAM macro may exist. The optimal write pulse width depends on both the device and the architecture specifications. The impact of process variations including the MTJ and the FinFET access transistor are also analyzed. © 2015 IEEE.

We investigate the possibility of realizing a spintronic memristive device based on the dependence of the tunnel conductance on the relative angle between the magnetization of the two magnetic electrodes in in-plane magnetized tunnel junctions. For this, it is necessary to design a free layer whose magnetization can be stabilized along several or even any in-plane direction between the parallel and the antiparallel magnetic configurations. We experimentally show that this can be achieved by exploiting antiferromagnet-ferromagnet exchange interactions in a regime where the antiferromagnet is thin enough to induce enhanced coercivity and no exchange bias. The frustration of exchange interactions at the interfaces due to competing ferro- and antiferromagnetic interactions is at the origin of an isotropic dissipation mechanism yielding isotropic coercivity. From a modeling point of view, it is shown that this isotropic dissipation can be described by a dry friction term in the Landau-Lifshitz-Gilbert equation. The influence of this dry friction term on the magnetization dynamics of an in-plane magnetized layer submitted to a rotating in-plane field is investigated both analytically and numerically. The possibility to control the free layer magnetization orientation in an in-plane magnetized magnetic tunnel junction by using the spin transfer torque from an additional perpendicular polarizer is also investigated through macrospin simulation. It is shown that the memristor function can be achieved by the injection of current pulses through the stack in the presence of an in-plane static field transverse to the reference layer magnetization, the aim of which is to limit the magnetization rotation between 0{\deg} and 180{\deg}.

Spin-transfer torque random access memory (STT-RAM) is a fast, scalable, durable non-volatile memory which can be embedded into standard CMOS process. A wide range of write speeds from 1ns to 100ns have been reported for STT-RAM. The switching current of magnetic tunnel junction (MTJ) (which is the storage element of STT-RAM) is inversely proportional to the write pulse width. In this work, we propose a methodology to design STT-RAM for different optimization goals such as read performance, write performance and write energy by leveraging the trade-off between write current and write time of MTJ. We take the typical in-plane MTJ and advanced perpendicular MTJ (PMTJ) as our optimization targets. Our study shows that reducing write pulse width will harm read latency and energy. It is observed that sweet spots of write pulse width which minimize the write energy or write latency of STT-RAM caches may exist. The optimal write pulse width depends on MTJ specifications, STT-RAM capacity and I/O width. The simulation results indicate that by utilizing PMTJ, the optimized STT-RAM can compete against SRAM and DRAM as universal memory replacement in low power embedded systems.

As CMOS technology scales down to the nanoscale, high leakage power consumption becomes one of the major concerns in the design of electronic circuits. To overcome this challenge, nano-emerging technologies and logic-in-memory (LIM) structures are being studied. Magnetic tunnel junction (MTJ) is an emerging spin-based device, which consumes very minimal leakage power in conjunction with CMOS transistors. In this paper, we propose a novel MTJ/CMOS design, which consumes low power and has lower delay than the existing LIM-based MTJ/CMOS designs. The proposed MTJ/CMOS designs have lower power and lower delay by charge sharing the output nodes during the pre-charge phase. The designs are simulated using 45 nm CMOS technology with perpendicular anistropy CoFeB/MgO MTJ model using a Cadence Spectre simulator. From the simulation results, we can see that the proposed MTJ/CMOS OR, AND, XOR, MUX, and full adder designs have 31.35%, 40.15%, 49.17%, 35.86%, and 42.62% lower power-delay-product, respectively, compared with the existing MTJ/CMOS designs. Furthermore, in this paper, we have also studied the usage of integrating nano-electronic devices, such as a carbon nanotube field-effect transistor and a Fin field-effect transistor, in the proposed circuits along with the MTJ devices.

Spin Transfer Torque (STT) switching realized using a Magnetic Tunnel Junction (MTJ) device has shown great potential for low power and non-volatile storage. A prime application of MTJs is in building non-volatile Look Up Tables (LUT) used in reconfigurable logic. Such LUTs use a hybrid integration of CMOS transistors and MTJ devices. This paper discusses the reliability of STT based LUTs under transistor and MTJ variations in nano-scale. The sources of process variations include both the CMOS device related variations and the MTJ variations. A key part of the STT based LUTs is the sense amplifier needed for reading out the MTJ state. We compare the voltage and current based sensing schemes in terms of the power, performance, and reliability metrics. Based on our simulation results in a 16nm CMOS, for the same total device area, the voltage mode sensing scheme offers 75% lower failure rates under threshold voltage (Vth) variations, 4.9X higher tolerance to MTJ resistance variations, 19% less delay, and 64% lower active power compared to the current sensing scheme.

Double magnetic tunnel junction two bit memory and nonvolatile logic for in situ computing

Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging

Recently, experimental results have demonstrated that perpendicular magnetic tunnel junction (p-MTJ) with the antiferromagnetic(AFM)/ferromagnetic (FM)/oxide structure can achieve field-free spin-orbit torque (SOT) switching since the AFM metal strip can not only generate the SOT, but also provide an exchange bias (HEX), making it suitable for practical applications. However, owing to that the HEX is weak, such field-free SOT switching is incomplete, thus resulting in severe switching reliability. In addition, a large SOT switching current (ISOT) is also required, leading to high switching energy dissipation. In this paper, to address these issues, the voltage-controlled magnetic anisotropy (VCMA) is introduced to assist the SOT switching, and such novel switching method is referred as voltage-gated SOT (VGSOT). First, we develop a physics-based compact model for the three-terminal VGSOT-MTJ device, which includes three modules, i.e., the electrical module, the tunnel magnetoresistance module and the dynamic switching module. Then, the impact of the VCMA effect on the field-free SOT switching is investigated by solving a modified Landau-Lifshitz-Gilbert (LLG) equation with consideration of the VCMA, SOT and HEX. Simulation results show that thanks to the introduction of the VCMA effect, the critical ISOT can be reduced greatly, and the incomplete field-free SOT switching can be completed. With further analysis, we obtain a special switching condition, under which complete SOT field-free switching can be achieved with a shortest path and ultra-low power. Moreover, a novel write pulse scheme is proposed to achieve high speed and reliability.

We present a theoretical simulation to calculate the tunnel magnetoresistance (TMR) in magnetic tunnel junction with embedded nano-particles (npMTJ). The simulation is done in the range of coherent electron tunneling model through the insulating layer with embedded magnetic and non-magnetic nano-particles (NPs). We consider two conduction channels in parallel within one MTJ cell, in which one is through double barriers with NP (path I in Fig. 1) and another is through a single barrier (path II). The model allows us to reproduce the TMR dependencies at low temperatures of the experimental results for npMTJs [2-4] having in-plane magnetic anisotropy. In our model we can reproduce the anomalous bias-dependence of TMR and enhanced TMR with magnetic and non-magnetic NPs. We found that the electron transport through NPs is similar to coherent one for double barrier magnetic tunnel junction (DMTJ) [1]; therefore, we take into account all transmitting electron trajectories and the spin-dependent momentum conservation law in a similar way as for DMTJs. The formula of the conductance for parallel (P) and anti-parallel (AP) magnetic configurations is presented as following: G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P(AP)</sup> = G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> σk <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F, s</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /4π ∫ Cos (θ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> ) D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P(AP)</sup> Sin(θ)dθ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> dφ, where Cos(θ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> ) is cosine of incidence angle of the electron trajectory θ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> , with spin index s=(↑,↓), k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F, s</sub> , is the Fermi wave-vector of the top (bottom) ferromagnetic layers; for simplicity the top and bottom ferromagnetic layers are taken as symmetric; G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> =2e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /h and σ is area of the tunneling cell. The transmission probability D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P(AP)</sup> depends on diameter of NP (d), effective mass m and wave-vector of the electron k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NP</sub> attributing to the quantum state on NP (corresponding to the k-vector of the middle layer in DMTJs [1], and which is affected by applied bias V). Furthermore D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P(AP</sup> ) depends on Cos(θ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> ), k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F, s</sub> , barriers heights U <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1,2</sub> and widths L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1,2</sub> , respectively. The exact quantum mechanical solution for symmetric DMTJ was found in Ref.[1]. Here we employ parallel circuit connection of the tunneling unit cells, where each cell contains one NP with the average d less than 3 nm per unit cell's area (σ =20 nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), while tunnel junction itself has surface area S and consists of N cells (N=S/σ). The total conductance of the junction is G = Nx (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1↑</sub> +G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ↑+G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1↓</sub> +G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ↓), where G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1, s</sub> is dominant conductance with the NP (path I), G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2, s</sub> is conductance of the direct tunneling through the single barrier (path II), and TMR=(G <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</sup> -G <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AP</sup> )/G <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AP</sup> ×100%.

The development of a scalable and user-friendly SPICE model is a key aspect of exploring the potential of spin-transfer torque MRAM (STT-MRAM). A self-contained magnetic tunnel junction (MTJ) SPICE model is proposed in this work which can reproduce realistic MTJ characteristics based on user-defined input parameters such as the free layer's length, width, and thickness. Using the propose model, scalability studies of both in-plane and perpendicular MTJs can be performed across different technology nodes with minimal effort, which differentiates this model from most previously reported models.

Magnetoresistive memory (MRAM) is one of the forerunners of the nanotechnology enabled memories lined to replace the traditional memories like Flash, DRAM and SRAM. MRAMs are based on the phenomenon of spin dependent tunneling in magnetic tunnel junctions (MTJs). It stores data in the magnetization of a magnetic layer as opposed to electrical charge in conventional RAMs. Yet the read-out of MRAM is electrical. It is claimed to offer something close to the speed of SRAM, with a density approaching that of single-transistor DRAM and the ability to store information when power is removed, like flash memory or EEPROM. This paper works out the microstructure processing steps in the fabrication of an MTJ based MRAM cell in two distinct versions. The technicalities of the two MTJ based MRAM cell configurations have been discussed in this paper. The I-V characteristics and TMR ratios of the widely investigated Fe/MgO/Fe magnetic tunnel junction have also been evaluated using first principle LSDA band-structure calculations. Micro magnetic simulations of the MTJ demonstrate the magnetic switching in the two ferromagnetic layers. The resulting hysteresis loop has been presented at the end of the paper.

Among the beyond-complementary metal-oxide- semiconductor (CMOS) devices being explored, ferroelectric field-effect transistors (FeFETs) are considered as one of the most promising. FeFETs are being studied by all major semiconductor manufacturers, and experimentally, FeFETs are making rapid progress. FeFETs also stand out with the unique hysteretic Ids-Vgs characteristic that allows a device to function as both a switch and a nonvolatile (NV) storage element. We exploit this FeFET property to build two categories of fine-grained logic-in-memory (LiM) circuits: 1) ternary content addressable memory (TCAM) which integrates efficient and compact logic/processing elements into various levels of memory hierarchy; 2) basic logic function units for constructing larger and more complex LiM circuits. Two writing schemes (with and without negative supply voltages respectively) for FeFETs are introduced in our LiM designs. The resulting designs are compared with existing LiM approaches based on CMOS, magnetic tunnel junctions (MTJs), resistive random access memories (ReRAMs), ferrorelectric tunnel junctions (FTJs), etc., that afford the same circuit-level functionality. Simulation results show that FeFET-based NV TCAMs offer lower area overhead than MTJ (79%) and CMOS (42% less) equivalents, as well as better search energy-delay products (EDPs) than TCAM designs based on MTJ (149×), ReRAM (1.7×), and CMOS (1.3×) in array evaluations. NV FeFET-based LiM basic circuit blocks are also more efficient than functional equivalents based on MTJs in terms of propagation delay (4.2×) and dynamic power (2.5×). A case study for an FeFET-based LiM accumulator further demonstrates that by employing FeFET as both a switch and an NV storage element, the FeFET-based accumulator can save area (36%) and power consumption (40%) when compared with a conventional CMOS accumulator with the same structure.