Vector spin modeling for magnetic tunnel junctions with voltage dependent effects

As the memory market becomes more diverse, the conventional memory hierarchies composed of Flash memory, DRAM and SRAM are now being asked to have various and segmented system to fill the gap between the current memory systems in terms of the cost and performance. The nonvolatile memory will upgrade the current memory subsystems and enable the stable system architectures that retain their state even when power is off. The emerging memories will not directly replace the existing memory (DRAM and Flash memory) but will make a new memory class. The attributes of STT-MRAM can lead to adopt in-memory computing architectures for the embedded memory solution SoC. In these circumstances, the accurate and scalable model of magnetic tunnel junction (MTJ) is required to accelerate the commercialization of STT-MRAM. In this thesis, after the MTJ basics is introduced as a storage element and the magnetic dynamics to utilize the electron spins as wells as the electron charges, the parallel and anti-parallel magnetization configuration is explained in terms of the band structure to understand the basic operation of the MTJ in memory cell. To demonstrate the viability of MTJ as a memory cell, the switching mechanism, reading/writing scheme, and some important parameters in STT-MRAMs such as TMR (Tunneling Magnetoresistance), Switching current (Ic), and Thermal Stability (Δ) are investigated. As a test vehicle of the technology, a set of RAM is designed in this research to show its efficiency and advantages of MTJ memory cell. As a first step of the design, the scalable model of a MTJ that accurately depicts the spin-transfer torque dynamic switching behavior of a MTJ is verified along with its bias voltage and Temperature dependency. The model integrates the physical models of static and dynamic behaviors; many experimental parameters are provided to see the process variations, especially temperature and bias voltage perspective. Based on the verified model, a set of RAM circuit is designed, and the designed STT-MRAM circuit's behavior and performances are analyzed to find the optimum tunnel magnetoresistance (TMR) ratio and switching performance. Of the compact model of the CoFeB/MgO PMA-MTJ (perpendicular magnetic anisotropy MTJ). The whole circuit was designed in a standard 45nm CMOS technology using MTJ. The measurement shows that the switching delay of MTJ increases by 5.5ns with growing tunnel barrier oxide (MgO) thickness from 0.85nm to 1.15nm. A bit longer delay for writing is observed as expected. The simulation shows a trade-off between memory access time and MTJ area as the switching delay of MTJ decreases by 6.5ns when the MTJ area increases from 1010nm to 4040nm. For reading operation of the memory, the conventional sense amplifier circuit is employed to detect the stored bit-cell. In the reading peripheral circuits including sense amplifier, the fixed reference voltage (0.9V) is used to simplify the analysis. The reading operation and peripheral block of memory circuits is verified successfully with read access time of 1.47ns.--Author's abstract

Recently, there has been a growing interest in the thermal stability in magnetic tunnel junction (MTJ) devices with an aspect of the temperature increment during current-induced magnetization switching (CIMS) process. In this work, the temperature increment is explored with factors of the tile of the initial magnetization direction in free layer, θ0, and the MgO layer thickness for different pulse durations, tp. The results show that the highest temperature in MTJ nanopillar is significant at the θ0 of1°-5° and the pulse duration tp < 0.4 ns. Moreover, the temperature results with decreasing the MgO layer thickness are not considerable difference at θ0 of1°-5° for the same tp.

Spin Transfer Torque (STT) switching realized using a Magnetic Tunnel Junction (MTJ) device has shown great potential for low power and non-volatile storage. A prime application of MTJs is in building non-volatile Look Up Tables (LUT) used in reconfigurable logic. Such LUTs use a hybrid integration of CMOS transistors and MTJ devices. This paper discusses the reliability of STT based LUTs under transistor and MTJ variations in nano-scale. The sources of process variations include both the CMOS device related variations and the MTJ variations. A key part of the STT based LUTs is the sense amplifier needed for reading out the MTJ state. We compare the voltage and current based sensing schemes in terms of the power, performance, and reliability metrics. Based on our simulation results in a 16nm CMOS, for the same total device area, the voltage mode sensing scheme offers 75% lower failure rates under threshold voltage (Vth) variations, 4.9X higher tolerance to MTJ resistance variations, 19% less delay, and 64% lower active power compared to the current sensing scheme.

The development of energy-efficient neural network hardware using magnetic tunnel junction (MTJ) devices has been widely investigated. One of the issues in the use of MTJ devices is large write energy. Since MTJ devices show stochastic behaviors, a large write current with enough time length is required to guarantee the certainty of the information held in MTJ devices. This paper demonstrates that quantized neural networks (QNNs) exhibit high tolerance to bit errors in weights and an output feature map. Since probabilistic switching errors in MTJ devices do not have always a serious effect on the performance of QNNs, large write energy is not required for reliable switching operations of MTJ devices. Based on the evaluation results, we achieve about 80% write-energy reduction on buffer memory compared to the conventional method. In addition, it is demonstrated that binary representation exhibits higher bit-error tolerance than the other data representations in the range of large error rates.

Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging

This paper describes a robust, modular, and physics-based circuit framework to model the conventional and emerging magnetic tunnel junction (MTJ) devices. Magnetization dynamics are described by the stochastic Landau-Lifshitz-Gilbert (sLLG) equation whose results are rigorously benchmarked with a Fokker-Planck equation description of the magnet dynamics. We then show how sLLG is coupled to the transport equations of MTJ-based devices in a unified circuit platform. Step by step, we illustrate how the physics-based MTJ model can be extended to include different spintronics phenomena, including spin-transfer torque, voltage-controlled magnetic anisotropy (VCMA), and spin-orbit torque phenomena by the experimentally benchmarked examples. To demonstrate how our approach can be used in the exploration of novel MTJ-based devices, we present a recently proposed MEMS resonator-driven spin-torque nano-oscillator (STNO) that can reduce the phase noise of STNOs. We briefly elaborate on the use of our framework beyond conventional devices.

As CMOS technology scales down to the nanoscale, high leakage power consumption becomes one of the major concerns in the design of electronic circuits. To overcome this challenge, nano-emerging technologies and logic-in-memory (LIM) structures are being studied. Magnetic tunnel junction (MTJ) is an emerging spin-based device, which consumes very minimal leakage power in conjunction with CMOS transistors. In this paper, we propose a novel MTJ/CMOS design, which consumes low power and has lower delay than the existing LIM-based MTJ/CMOS designs. The proposed MTJ/CMOS designs have lower power and lower delay by charge sharing the output nodes during the pre-charge phase. The designs are simulated using 45 nm CMOS technology with perpendicular anistropy CoFeB/MgO MTJ model using a Cadence Spectre simulator. From the simulation results, we can see that the proposed MTJ/CMOS OR, AND, XOR, MUX, and full adder designs have 31.35%, 40.15%, 49.17%, 35.86%, and 42.62% lower power-delay-product, respectively, compared with the existing MTJ/CMOS designs. Furthermore, in this paper, we have also studied the usage of integrating nano-electronic devices, such as a carbon nanotube field-effect transistor and a Fin field-effect transistor, in the proposed circuits along with the MTJ devices.

Energy dissipation in integrated circuits has become a matter of grave concern. Various approaches at different levels of abstraction such as logic-in-memory structures based on magnetic tunnel junction (MTJ) devices and approximate computing can be employed to reduce energy consumption. Efficient hybrid MTJ/FinFET designs for exact and approximate 5:2 compressors are proposed herein. The proposed designs use the spin Hall effect (SHE)-assisted writing method to store data in MTJs, which significantly improves the energy efficiency of the MTJ switching as compared with the conventional spin transfer torque (STT) method. The circuits are simulated in HSPICE using 7-nm FinFET and SHE perpendicular MTJ models. The results indicate that the proposed approximate designs provide significant improvements in terms of energy consumption and device count compared with their exact counterpart. The first and second proposed approximate designs improve the power consumption by 51%, read delay by 16% and 26%, and transistor count by 63% and 70%, respectively, as compared with the exact design. The second approximate compressor offers a significantly lower error rate (27% versus 48%) in comparison with the first approximate design, as well as better performance parameters. The imprecise 5:2 compressors are used in image processing applications to assess their accuracy metrics. Comprehensive MATLAB simulations indicate that the proposed approach provides great capabilities for image processing applications considering various accuracy and quality metrics.

A novel process for highly manufacturable MRAM

Magnetic tunnel junction (MTJ) device, a nonvolatile spintronics device, draws wide attention for its low current drive, non-volatility, small size, infinite erasure, and low standby power. It is widely used in magnetic random-access memory (MRAM) or embedded in CMOS logical circuits. In this paper, a novel high speed, low resource and non-volatile MTJ-CMOS hybrid logical circuit structure is proposed, which consists of Multi-Voltage controlled Multi-Write (MVMW) write circuit and High-Speed Sense Amplifier (HSSA) circuit. The MVMW write circuit enhances the write speed by shortening the critical path while achieving two independent write controls of the MTJs. Also, a voltage comparator sense amplifier is employed to increase the read speed (about 110ps). By using a dynamic compact MTJ model and 55 nm CMOS design kit, we designed a circuit architecture which can be used to form all kinds of logical computations. An AND/NAND logical is used to demonstrate functionality of the architecture and compared it with a traditional MTJ-CMOS hybrid circuit. The proposed non-volatile MTJ-CMOS hybrid circuit uses only 62.5% of resources, achieving a 4.37X write speed and a 2.64X read speed. The overall average speed increases 3.12 times with similar power consumption. Moreover, it is compatible for asynchronous circuits design.

Identifying manufacturing defects in magnetic tunnel junction (MTJ) device is crucial for the yield and reliability of spin-torque-transfer (STT) magnetic random-access memory (MRAM) arrays. Several of the MTJ defects result inparametric deviations of the device that deteriorate over time. In this article, we present the design-for-testability (DFT) scheme for monitoring the electrical parameter deviations occurring due to the defect formation over time. A programmable DFT scheme was implemented for a subarray in 65-nm CMOS technology to evaluate the feasibility of the test scheme. The scheme utilizes the read sense path to compare the bit-cell electrical parameters against known DFT cell's characteristics. Built-in-self-test (BIST) methodology is utilized to trigger the onset of the fault once the device parameter crosses a threshold value. We demonstrate the operation and evaluate the accuracy of detection with the proposed scheme. The DFT scheme can be exploited for monitoring aging defects, modeling their behavior and optimization of the fabrication process.

The quest for highly efficient cognitive computing has led to extensive research interest for the field of neuromorphic computing. Neuromorphic computing aims to mimic the behavior of biological neurons and synapses using solid-state devices and circuits. Among various approaches, emerging non-volatile memory technologies are of special interest for mimicking neuro-synaptic behavior. These devices allow the mapping of the rich dynamics of biological neurons and synapses onto their intrinsic device physics. In this letter, we focus on Spike Timing Dependent Plasticity (STDP) behavior of biological synapses and propose a method to implement the STDP behavior in Magnetic Tunnel Junction (MTJ) devices. Specifically, we exploit the time-dependent heat dynamics and the response of an MTJ to the instantaneous temperature to imitate the STDP behavior. Our simulations, based on a macro-spin model for magnetization dynamics, show that, STDP can be imitated in stochastic magnetic tunnel junctions by applying simple voltage waveforms as the spiking response of pre- and post-neurons across an MTJ device.

Spiking neural networks (SNNs) are of interest for applications for which conventional computing suffers from the nearly insurmountable memory-processor bottleneck. This paper presents a stochastic SNN architecture that is based on specialized logic-in-memory synaptic units to create a unique processing system that offers massively parallel processing power. Our proposed synaptic unit consists of strained magnetic tunnel junction (MTJ) devices and transistors. MTJs in our synapse are dual purpose, used as both random bit generators and as general-purpose memory. Our neurons are modeled as integrate-and-fire components with thresholding and refraction. Our circuit is implemented using CMOS 28-nm technology that is compatible with the MTJ technology. Our design shows that the required area for the proposed synapse is only [Formula: see text]. When idle, the synapse consumes 675 pW. When firing, the energy required to propagate a spike is 8.87 fJ. We then demonstrate an SNN that learns (without supervision) and classifies handwritten digits of the MNIST database. Simulation results show that our network presents high classification efficiency even in the presence of fabrication variability.

We derive expressions for both parallel and perpendicular components of spin transfer torque (STT) in magnetic tunnel junctions (MTJs), which have several important advantages over the currently available expressions: First they are derived in a more realistic approximation, resulting in excellent agreement with exact results even in the presence of resonant tunneling. Second, we show that they can be expressed in terms of the scattering matrix elements, which gives them a clear physical interpretation. Third, they are given entirely in terms of collinear quantities, which are readily available in existing transport codes. We use these expressions to investigate STT behavior in MTJs with asymmetric barriers at finite bias. The results show that lowering the barrier height in the bulk does not qualitatively change the behavior of STT. The absolute STT increases on account of the overall increase of the barrier transparency; however, the STT efficiency remains in the same range. At the same time, modifications of the interfaces can qualitatively change STT behavior. Thus, interface engineering can be used to control the bias dependence of STT and optimize the performance of STT-based devices.

Magnetoresistive random access memory (MRAM) technology combines a spintronic device with standard silicon-based microelectronics to obtain a combination of attributes not found in any other memory technology. Key attributes of MRAM technology are nonvolatility and unlimited read and write endurance. Magnetic tunnel junction (MTJ) devices have several advantages over other magnetoresistive devices for use in MRAM cells, such as a large signal for the read operation and a resistance that can be tailored to the circuit. Due to these attributes, MTJ MRAM can operate at high speed and is expected to have competitive densities when commercialized. In this paper, we review our recent progress in the development of MTJ-MRAM technology. We describe how the memory operates, including significant aspects of reading, writing, and integration of the magnetic material with CMOS, which enabled our recent demonstration of a 1-Mbit memory chip. Important memory attributes are compared between MRAM and other memory technologies.