Analytic performance modeling for a spectrum of multithreaded processor architectures

Multiple, high-level operators are assigned to a general operand. The operators are implemented with individual micro-processors and are "attached" dynamically to the memory location representing the "current" value of the operand. The operators then asynchronously use each new operand value as it is stored and perform their operations in parallel. The proposed architecture represents a true M I S D (Multiple Instruction Stream - Single Data Stream) computer. Its architecture can provide effective parallelism and reduced programming complexity for a large class of both numeric and non-numeric computer problems.

Author describes military and special supercomputer centers and networks by example CT-2. Work on highly productive and promising SC with a globally addressable memory and multi-thread architecture is carried out within the framework of the CT-2 project. The eponymous supercomputer belongs to the class of strategic supercomputers. The code name used is CT-2 (full name Qin Tao -2) - this is the idiom in the Chinese name “The main project in the interests of special studies of military intelligence of the Ministry of Defense of China”. Due to using of massive multi-thread streaming architecture increased tolerance to delays in performing operations with memory and the network, effectively support working with program models in the form of static graphs of data flows. Because of this, it will successfully cope with the processing in real time of multiple data streams and work effectively through a single address space with a huge memory capacity of several tens of petabytes, even in the mode of intensive irregular work with it, it will have exceptional fault tolerance and availability. The amount of available memory for the user program is 32PB, the physical memory is 64PB, which is done for hot standby. According to information received in 2011, the initially massive multi-thread microprocessor CT-2 with asynchronous threads for information systems has also become hybrid, it has enhanced numerical processing power - SIMD operations on short vectors have been introduced, as well as elements of modern graphic processors in the form of synchronous threads.

9 - Parallel Processors

A parallelized point rowwise successive over-relaxation method on a multiprocessor

This paper presents an integrated compiler, runtime control, and hardware solution to improve inter-thread communication and synchronization in a multithreaded processor architecture. Multithreading improves processor utilization by exploiting more parallelism. The improvement in utilization, however, is hindered by interthread communication and synchronization problems, which incur extra communication overhead and thus degrade the performance of the system. In this paper, we propose efficient inter-thread communication and synchronization schemes based on a superscalar DLX processor with multithreading functionality. Compiler, runtime control, and hardware support used in the schemes are discussed. Simulations are presented to show the effectiveness of the proposed schemes.

Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents our investigation into ways to modify MIMD architectures to allow them to extract the instruction level parallelism achieved by current superscalar and VLIW machines. A new architecture is proposed which utilizes the advantages of a multiple instruction stream design while addressing some of the limitations that have prevented MIMD architectures from performing ILP operation. A new code scheduling mechanism is described to support this new architecture by partitioning instructions across multiple processing elements in order to exploit this level of parallelism.

Algorithm for solving tridiagonal matrix problems in parallel

This paper presents a parallelization workflow in model-based development for a MIMD (Multiple Instruction streams, Multiple Data streams) processor with a vector accelerator. In the workflow, an Integer Linear Programming (ILP) formulation is proposed to deploy tasks extracted from the Simulink model. The proposed formulation can determine the number of processors that a task needs, and whether vectorization should be used to accelerate a task to reduce synchronization overhead and execution time. In the experiments, a MATLAB script was used to simulate the ILP formulation with randomly generated task graphs and evaluate its performance. Furthermore, we applied ILP task mapping to a real-world Model Predictive Control (MPC) application on DR1000C, a type of RISC-V MIMD processor with a vector accelerator. The maximum speedup of 10. 05x is obtained, which is promising for use in real-time embedded systems.

A simultaneous multithreading multicore processor is proposed to accelerate object recognition for 720p HD video streams. The multithreading architecture with Q-learning based dynamic resource management enables concurrent processing of 8 region-of-interests with 5-stage fine grained recognition pipeline outperforming previous object recognition processors with 342GOPS computing power. In addition, the dynamic resource management contributes to increase of energy efficiency by applying the on-line learning DVFS and dynamic tile allocation based on task variance and hardware utilization to achieve 9.6mJ/frame with 1280×720 pixel image. It achieves 2.72× throughput and 3.7× energy efficiency compared to previous recognition processors.

This paper presents a mechanism to dynamically detect the loops that are executed in a program. This technique detects the beginning and the termination of the iterations and executions of the loops without compiler/user intervention. We propose to apply this dynamic loop detection to the speculation of multiple threads of control dynamically obtained from a sequential program. Based an the highly predictable behavior of the loops, the history of the past executed loops is used to speculate the future instruction sequence. The overall objective is to dynamically obtain coarse grain parallelism (at the thread level) that can be exploited by a multithreaded architecture. We show that for a 4-context multithreaded processor the speculation mechanism provides around 2.6 concurrent threads in average.

This paper presents a multithreaded processor architecture for massively parallel computers, and presents RICA-1 multithreaded processor based on it. RICA-1 provides fairly efficient mechanisms of message reception, thread invocation, message generation/transmission and synchronization. It provides simple communication pipelines. Computation pipelines and communication pipelines are highly fused within a processor architecture. Parallel primitives such as remote memory access, remote procedure call and synchronizations are efficiently performed by RICA-1. The first version of RICA-1 is being implemented by a CMOS standard cell chip with 200 K random gates and 13 KB internal RAMs. It is packed into the 527 pin CPGA package and will operate with a 50 MHz clock in August 1996. In RICA-1, communication pipelines and the RISC-type execution pipelines are highly fused by a simple sequencer and three sets of register files substantially reduces the thread switch overhead.

Simultaneous Multithreading machines fetch and execute instructions from multiple instruction streams to increase system utilization and speedup the execution of jobs. When there are more jobs in the system than there is hardware to support simultaneous execution, the operating system scheduler must choose the set of jobs to coscheduleThis paper demonstrates that performance on a hardware multithreaded processor is sensitive to the set of jobs that are coscheduled by the operating system jobscheduler. Thus, the full benefits of SMT hardware can only be achieved if the scheduler is aware of thread interactions. Here, a mechanism is presented that allows the scheduler to significantly raise the performance of SMT architectures. This is done without any advance knowledge of a workload's characteristics, using sampling to identify jobs which run well together.We demonstrate an SMT jobscheduler called SOS. SOS combines an overhead-free sample phase which collects information about various possible schedules, and a symbiosis phase which uses that information to predict which schedule will provide the best performance. We show that a small sample of the possible schedules is sufficient to identify a good schedule quickly. On a system with random job arrivals and departures, response time is improved as much as 17% over a schedule which does not incorporate symbiosis.

The research about processor development was made to analyze the reasons of transition from increasing clock speed (gigahertz) to multi-threaded architecture. Main goal is to find out how the technological limits which is related to energy consumption, heat dispersion and CMOS upscaling principles, affected the CPU progression model.Key results: Assumed, that the yearly average productivity rate in single threaded mode was 11.2 percent, and in multi-threaded it was 25.2 percent. The performance parity between multi core and single core processors increased from 2.1 multiplication in 2007 to 19.6 multiplication in 2025. The major technological reasons are being limited in 3.8-4.0 gigahertz clock speed, exponential rise in power consumption, and the impossibility of further size reduction made multi core technology the only was forward for scaling.Conclusions: The trend towards multi thread processors is due to the fundamental limitations of silicon technology. The trend towards multi thread processors is due to the fundamental limitations of silicon technology. Multi-threaded processors give a significant improvement in computing capacity while keeping energy consumption in a reasonable level and accepting the requirements of modern applications. This tendency is predicted to continue into the 2030s.

Hardware multithreading is a common approach for tolerating memory latency by utilizing idle cycles and avoiding CPU stalling. Nowadays, multithreading architectures are commonly used across many processors and various embedded edge devices to improve performance. This work suggests a new multithreading in-order pipeline microarchitecture design for RISC-V and proposes an efficient event-based issue scheduling algorithm. The proposed scheduling algorithm is based on the unique RISC-V ISA that enables decoding of the instruction type in an early stage of the pipeline. The RISC-V-based multithreading architecture is evaluated using a dedicated software simulator. Simulation results show that the proposed algorithm outperforms the classical Round Robin and the coarse grain algorithms. The proposed architecture is evaluated using the standard MiBench benchmark and other common applications, demonstrating pipeline utilization improvement of up to about 26% in terms of IPC using four threads.

The classification of large amounts of data is a challenging problem that only a small number of classification algorithms can handle. In this paper we propose a Parallel Classification System based on an Ensemble of Mixture of Experts (PCEM). The system uses MIMD (Multiple Instruction and Multiple Data Stream) architecture, using a set of process that communicates via messages. PCEM is implemented using parallel schemes of traditional classifiers, for the mixture of experts, and using a parallel version of a Genetic Algorithm to implement a voting weighted criterion. The PCEM is a novel algorithm since it allows us to classify large amounts of data with low execution times and high performance measures, which makes it an excellent tool for in classification of large amounts of data. A series of tests were performed with well known databases that allowed us to measure how PCEM performs with many datasets and how well it does compared with other systems available.