Integrated support to improve inter-thread communication and synchronization in a multithreaded processor

The instruction-level parallelism found in a conventional instruction stream is limited. Studies have shown the limits of processor utilization even for today's superscalar microprocessors. One solution is the additional utilization of more coarse-grained parallelism. The main approaches are the (single) chip multiprocessor and the multithreaded processor which optimize the throughput of multiprogramming workloads rather than single-thread performance. The chip multiprocessor integrates two or more complete processors on a single chip. Every unit of a processor is duplicated and used independently of its copies on the chip. In contrast, the multithreaded processor is able to pursue two or more threads of control in parallel within the processor pipeline. Unused instruction slots, which arise from pipelined execution of single-threaded programs by a contemporary microprocessor, are filled by instructions of other threads within a multithreaded processor. The execution units are multiplexed between the threads in the register sets. Underutilization of a superscalar processor due to missing instruction-level parallelism can be overcome by simultaneous multithreading, where a processor can issue multiple instructions from multiple threads each cycle. Simultaneous multithreaded processors combine the multithreading technique with a wide-issue superscalar processor such that the full issue bandwidth is utilized by potentially issuing instructions from different threads simultaneously. This survey paper explains and classifies the various multithreading techniques in research and in commercial microprocessors and compares multithreaded processors with chip multiprocessors.

The throughput of pipelined processors suffers from delays associated with instruction dependencies and memory latencies. Multithreaded architectures attempt to hide such delays by sharing the processor with multiple instruction streams. In this paper we develop a comprehensive analytic framework to quantitatively evaluate the performance of a wide spectrum of mulithreaded machines, ranging from those that are capable of switching threads every cycle to those that switch threads only on long delays. The models are validated against previously published simulation and modeling results, and then used to assess the performance potential of multithreading given current processor technology. >

Multiprocessor‐on‐a‐chip is becoming possible due to progress in semiconductor technologies. In the multiprocessor, the threaded parallel processing requires decreasing the overhead of interthread communication and synchronization. We propose the tagged communication and synchronization memory with the access counter using CAM (TCSM) which supports a high‐speed mechanism for the mutual exclusion, the condition synchronization, the barrier synchronization, and the multicasting between the threads. TCSM allocates its entries dynamically and ensures the producer–consumer synchronization by valid/invalid state in the access count. The execution environment of the threads is protected because the tag of TCSM is used for identifying both the task which threads belong to and the storage used by threads. The MTA/TCSM multichip multiprocessor system has been developed to evaluate the multiprocessor‐on‐a‐chip including TCSM. As a result of the evaluation on MTA/TCSM, the overhead of interthread synchronization and communication using TCSM is lower than using the conventional shared memory. © 2001 Scripta Technica, Syst Comp Jpn, 32(4): 1–13, 2001

This paper presents a multithreaded processor architecture for massively parallel computers, and presents RICA-1 multithreaded processor based on it. RICA-1 provides fairly efficient mechanisms of message reception, thread invocation, message generation/transmission and synchronization. It provides simple communication pipelines. Computation pipelines and communication pipelines are highly fused within a processor architecture. Parallel primitives such as remote memory access, remote procedure call and synchronizations are efficiently performed by RICA-1. The first version of RICA-1 is being implemented by a CMOS standard cell chip with 200 K random gates and 13 KB internal RAMs. It is packed into the 527 pin CPGA package and will operate with a 50 MHz clock in August 1996. In RICA-1, communication pipelines and the RISC-type execution pipelines are highly fused by a simple sequencer and three sets of register files substantially reduces the thread switch overhead.

A simultaneous multithreading multicore processor is proposed to accelerate object recognition for 720p HD video streams. The multithreading architecture with Q-learning based dynamic resource management enables concurrent processing of 8 region-of-interests with 5-stage fine grained recognition pipeline outperforming previous object recognition processors with 342GOPS computing power. In addition, the dynamic resource management contributes to increase of energy efficiency by applying the on-line learning DVFS and dynamic tile allocation based on task variance and hardware utilization to achieve 9.6mJ/frame with 1280×720 pixel image. It achieves 2.72× throughput and 3.7× energy efficiency compared to previous recognition processors.

This paper presents a mechanism to dynamically detect the loops that are executed in a program. This technique detects the beginning and the termination of the iterations and executions of the loops without compiler/user intervention. We propose to apply this dynamic loop detection to the speculation of multiple threads of control dynamically obtained from a sequential program. Based an the highly predictable behavior of the loops, the history of the past executed loops is used to speculate the future instruction sequence. The overall objective is to dynamically obtain coarse grain parallelism (at the thread level) that can be exploited by a multithreaded architecture. We show that for a 4-context multithreaded processor the speculation mechanism provides around 2.6 concurrent threads in average.

This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor. While SMT has been studied extensively over the past 6 years, previous research has focused entirely on user-mode execution. However, many of the applications most amenable to multithreading technologies spend a significant fraction of their time in kernel code. A full understanding of the behavior of such workloads therefore requires execution and measurement of the operating system, as well as the application itself.To carry out this study, we (1) modified the Digital Unix 4.0d operating system to run on an SMT CPU, and (2) integrated our SMT Alpha instruction set simulator into the SimOS simulator to provide an execution environment. For an OS-intensive workload, we ran the multithreaded Apache Web server on an 8-context SMT. We compared Apache's user- and kernel-mode behavior to a standard multiprogrammed SPECInt workload, and compared the SMT processor to an out-of-order superscalar running both workloads. Overall, our results demonstrate the microarchitectural impact of an OS-intensive workload on an SMT processor and provide insight into the OS demands of the Apache Web server. The synergy between the SMT processor and Web and OS software produced a greater throughput gain over superscalar execution than seen on any previously examined workloads, including commercial databases and explicitly parallel programs.

The research about processor development was made to analyze the reasons of transition from increasing clock speed (gigahertz) to multi-threaded architecture. Main goal is to find out how the technological limits which is related to energy consumption, heat dispersion and CMOS upscaling principles, affected the CPU progression model.Key results: Assumed, that the yearly average productivity rate in single threaded mode was 11.2 percent, and in multi-threaded it was 25.2 percent. The performance parity between multi core and single core processors increased from 2.1 multiplication in 2007 to 19.6 multiplication in 2025. The major technological reasons are being limited in 3.8-4.0 gigahertz clock speed, exponential rise in power consumption, and the impossibility of further size reduction made multi core technology the only was forward for scaling.Conclusions: The trend towards multi thread processors is due to the fundamental limitations of silicon technology. The trend towards multi thread processors is due to the fundamental limitations of silicon technology. Multi-threaded processors give a significant improvement in computing capacity while keeping energy consumption in a reasonable level and accepting the requirements of modern applications. This tendency is predicted to continue into the 2030s.

In Speculative Multithreading, data dependence that limits the speedup of speculative parallelization needs to be resolved to achieve a high performance. This paper designs a synchronization execution model, with the support of compiler, to synchronize store and load instructions that frequently have data dependence on each other. We use hardware profiler to gather dependence violation information of memory data, and the profiler information is fed back to the compiler. The compiler analyzes the synchronization efficiency, select store/load pairs of great synchronization potential, and inserts synchronization instructions using insertion algorithm. Loop threads and non-loop threads can both be synchronized. The hardware support is also given in the paper. The experimental results show that the synchronization under the compiler support can effectively resolve some memory data dependence and improve the performance of the speculative execution.

The Precomputed-Branch architecture: Efficient branches with compiler support

Speculative multithreading is a technique that has been used to improve single thread performance. Speculative multithreading architectures for Chip multiprocessors (CMPs) have been extensively studied. But there have been relatively few studies on the design of speculative multithreading for simultaneous multithreading (SMT) processors. The current SMT based designs – IMT [9] and DMT [2] use load/store queue (LSQ) to perform dependence checking. Since the size of the LSQ is limited, this design is suitable only for small threads. In this paper we present a novel cache-based architecture support for speculative simultaneous multithreading which can efficiently handle larger threads. In our architecture, the associativity in the cache is used to buffer speculative values. Our 4-thread architecture can achieve about 15% speedup when compared to the equivalent superscalar processors and about 3% speedup on the average over the LSQ-based architectures, however, with a less complex hardware. Also our scheme can perform 14% better than the LSQ-based scheme for larger threads.

In wireless sensor networks, efficient usage of energy helps in improving the network lifetime. Many power saving MAC schemes based on TDMA have been proposed in recent years, but none of them particularly discuss the problem of time synchronization. As there are many time synchronization algorithms have been proposed, but they can't be applied to these TDMA MAC schemes directly. In this paper, a lightweight and energy efficient time synchronization (LEETS) scheme that can be applied to all kinds of TDMA power saving MAC schemes was proposed. In the scheme, nodes compete the first slot of each time frame to broadcast local time information, which can be used to realize whole network synchronization. And guard interval is inserted in two consecutive slots to avoid collision may be caused by synchronization errors. The scheme has been simulated and the results show LEETS needs less message exchanges to realize synchronization than other time synchronization schemes. So, It is lightweight and energy efficient.

Real-time execution of applications is one of key requirements for Cyber-Physical Systems (CPS) that integrate computational and physical elements for our social infrastructure, such as robotics, transportation, and consumer appliances. In such real-time systems, a task must be executed so as not to violate given time constraints. Moreover, it is desirable that the execution time of the task is predictable precisely. When Out-of-Order (OoO) execution is adopted for real-time systems to enhance the performance, it is much difficult to predict execution time because of the feature of OoO execution. In order to deal with this problem, various schemes were proposed such as IPC control mechanism of Responsive Multithreaded (RMT) Processor. RMT Processor is a real-time microprocessor adopting simultaneous multithreading (SMT) architecture with OoO execution. Its IPC control mechanism which tries to adjust the number of instruction commits to meet a given target IPC. The IPC control scheme can be implemented not only on RMT Processor but also on various processors and can improve the predictability of execution time. However, if an error between target and actual IPCs is observed, it cannot cancel the error in the next control window, which is used in the control mechanism. Since such uncorrected errors are accumulated in the successive control window, the predictability of the execution time is degraded gradually. To overcome this problem, in this paper, we propose a thread speed control scheme for real-time microprocessors. This scheme is based on the IPC control mechanism on RMT Processor. Our proposed thread speed control scheme calculates an error between reference and actual IPCs, then it dynamically updates the reference IPC of the next control window in order to cancel the past errors. Our proposed scheme is designed and implemented on RMT Processor. The simulation results show that the error is reduced to 2.60 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> % in case that four threads are executed simultaneously.

MASA is a “first cut” at a processor architecture intended as a building block for a multiprocessor that can execute parallel Lisp programs efficiently. MASA features a tagged architecture, multiple contexts, fast trap handling, and a synchronization bit in every memory word. MASA's principal novelty is its use of multiple contexts both to support multithreaded execution —interleaved execution from separate instruction streams—and to speed up procedure calls and trap handling in the same manner as register windows. A project is under way to evaluate MASA-like architectures for executing programs written in Multilisp.

A multithreaded processor architecture enables fast context switching for tolerating memory access latency and bridging synchronization gap, and thus enables efficient utilization of execution pipelines. However, it cannot prevent all pipeline stalls; stalls will still occur when all processor built-in threads are in a wait state or there are not enough threads in a task to fill up all available context slots, since the mechanism for switching active threads is effective only for processor built-in contexts. In this paper, we propose an architecture that increases the virtual number of built-in contexts and enables seamless task switching by allocating and swapping task contexts hierarchically between processor and memory in a multitasking environment. At the same time, we aim at supporting real-time applications through hierarchical task allocation based on task priority and fast response mechanisms for interrupt requests exploiting the multiple-context architecture. Moreover, we propose two reconfigurable cache applications, a priority-based partitioning cache and a FIFO buffer, and their implementation methods. We have extended the general-purpose RISC processor architecture and are developing a new RISC core which can be used to implement the seamless task switching, fast response to interrupt requests, and the reconfigurable caches, for supporting real-time processing in a multi-tasking environment. we describe the design of the RISC core in this paper.