Application-aware group scheduler for Android

The quality of cloud computing services is evaluated based on various performance metrics out of which response time (RT) is most important. Nearly all cloud users demand its application's RT as minimum as possible, so to minimize overall system RT, the authors have proposed request response time prediction-based data center (DC) selection algorithm in this work. Proposed DC selection algorithm uses results of optimization function for DC selection formulated based on M/M/m queuing theory, as present cloud scenario roughly obeys M/M/m queuing model. In cloud environment, DC selection algorithms are assessed based on their performance in practice, rather than how they are supposed to be used. Hence, explained DC selection algorithm with various forecasting models is evaluated for minimum user application RT and RT prediction accuracy on various job arrival rates, real parallel workload types, and forecasting model training set length. Finally, performance of proposed DC selection algorithm with optimal forecasting model is compared with other DC selection algorithms on various cloud configurations.

This thesis presents a comprehensive study of tailored semiconductor devices that bridge conventional photodetection with neuromorphic photomemory applications through strategic engineering of response time characteristics. The fundamental insight underlying this work is that response time represents the critical parameter determining whether an optoelectronic device functions as a conventional photodetector or enables synaptic functionality for brain-inspired computing systems. The research demonstrates that the same physical mechanisms, such as photon absorption, carrier generation, charge transport, and recombination, can be optimized for dramatically different temporal characteristics, enabling devices that adapt their functionality based on operational requirements. Fast response times in the microsecond to millisecond range enable high-speed photodetection for telecommunications and sensing applications, while prolonged response times through persistent photoconductivity (PPC) spanning seconds to days enable the memory and learning functions essential for artificial synapses. The research contributions are organized into four interconnected studies that collectively demonstrate this dual functionality principle. Chapters 2 and 3 focus on optimizing devices for fast photodetection applications. Chapter 2 presents flexible germanium/titanium nitride (Ge/TiN) photodetectors that achieve enhanced near infrared responsivity through plasmonic enhancement and strain engineering, demonstrating how structural modifications can improve conventional photodetection performance while maintaining fast response characteristics. Chapter 3 investigates self powered silicon metal-semiconductor-metal (MSM) photodetectors utilizing asymmetric electrode configurations, achieving efficient photodetection without external bias through engineered Schottky barrier heights. Chapters 4 and 5 shift focus on exploiting extended response times for neuromorphic applications. Chapter 4 demonstrates silicon/indium gallium zinc oxide (Si/IGZO) photomemory devices with persistent photoconductivity exceeding nine days, achieved through substrate conductivity engineering that optimizes band alignment to trap photocarriers and prevent recombination. Chapter 5 presents transparent quartz/IGZO tracking devices that combine optical transparency with neuromorphic functionality, enabling covert trajectory monitoring through synaptic plasticity behaviors. The connection between these studies lies in the systematic exploration of how response time engineering enables the same semiconductor materials to serve two different purposes. The Ge/TiN and Si photodetectors in Chapters 2-3 are optimized for response times in the millisecond range, suitable for high-speed optical communication and imaging applications. In contrast, the IGZO-based devices in Chapters 4-5 exploit response times spanning minutes to days, enabling synaptic behaviors including PPF, learning-forgetting-relearning cycles, and long-term memory retention. All four device systems are based on MSM-type architectures that share the same fundamental band-to band excitation and carrier transport principles, and flexibility, self-powered operation, photomemory, and trajectory tracking are employed as representative manifestations of fast and slow response-time engineering within this common framework. The research provides new insights into the mechanisms controlling persistent photoconductivity, demonstrates practical strategies for substrate and interface engineering, and establishes design principles for next-generation neuromorphic optoelectronic systems. The significance of this research extends beyond individual device performance improvements to establish a fundamental framework for engineering semiconductor devices with tunable temporal characteristics. By demonstrating that the same materials and fabrication processes can yield devices optimized for either fast photodetection or extended photomemory functions, this work opens new possibilities for semiconductor devices with tunable temporal characteristics and design-level flexibility in their functional role.

Using cache-like architectural components including data caches, instruction caches, or branch target buffers as a side channel, software cache-based side-channel attacks are able to derive secret keys used in cryptographic operations through legitimate software activities. Existing software solutions are typically application specific and incur substantial performance overhead. Recent hardware proposals against attacks on data caches, although effective in reducing performance overhead, may still be vulnerable to advanced attacks. Furthermore, efficient defenses against attacks on other cache structures, including instruction caches and branch target buffers, are missing. In this paper, we propose hardware-software integrated approaches to defend against software cache-based attacks comprehensively. For attacks on data caches, we propose to use preloading, informing loads, and informing loads with software random permutation to secure the partition-locked cache (PLcache), the random permutation (RPcache) and regular caches, respectively. These approaches present different tradeoffs between hardware complexity and performance overhead. To defend against attacks on instruction caches, we show that the PLcache with preloading and the RPcache provide good protection. To defend against attacks based on branch target buffers, we propose to adopt a new update policy to eliminate potential information leaking. Our experiments show that the proposed schemes not only provide strong security protection but also incur small performance overhead.

Current commodity operating systems allow a privileged user to run some programs in kernel mode by installing a kernel module or a device driver, but there isnpsilat an available method to verify the reliability of these programs. As a result, malware leverages this way to corrupt system services, defeat anti-malware and even get control of the whole system. It makes operating-system-based security tools undergo all kinds of hardships in face of various attacks. Virtualization technology brings a new chance to protect operating systems out-of-box in hypervisors. This article proposes a system monitoring and controlling framework, named as BMCS, which monitors low-level states and hardware accessing events of operating system in a hypervisor. BMCS abstracts low-level states and events and profiles OS-level semantics with the help of a hosted daemon. Moreover, it can control the execution of operating system software through the hypervisor. Our out-of box method can collect real run-time operating system profile and control the execution of the OS according some defined rules. As a result, it makes the operating system stronger. We implement BMCS based on KVM and experiment results prove that BMCS performs well.

High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to use an optimizing compiler to minimize cache interference via an improved layout of the code. This technique, however, has been applied to application code only, even though there is evidence that the operating system often uses the cache heavily and with less uniform patterns than applications. Therefore, it is unknown how well existing optimizations perform for systems code and whether better optimizations can be found. We address this problem in this paper. This paper characterizes in detail the locality patterns of the operating system code and shows that there is substantial locality. Unfortunately, caches are not able to extract much of it: rarely-executed special-case code disrupts spatial locality, loops with few iterations that call routines make loop locality hard to exploit, and plenty of loop-less code hampers temporal locality. As a result, interference within popular execution paths dominates instruction cache misses. Based on our observations, we propose an algorithm to expose these localities and reduce interference. For a range of cache sizes, associativities, lines sizes, and other organizations we show that we reduce total instruction miss rates by 31-86% (up to 2.9 absolute points). Using a simple model this corresponds to execution time reductions in the order of 12-26%. In addition, our optimized operating system combines well with optimized or unoptimized applications. >

A real-time software MPEG1 video encoder on a multimedia RISC processor, V830R/AV, is presented. The V830R/AV processor provides 64-bit SIMD media-enhanced instructions. The motion estimation is accelerated by a combination of the partial absolute difference instruction and a method to sum up partial block differences. The IDCT in conformity with the IEEE standard is simply implemented by the multiply-accumulate instruction with symmetric rounding. The encoder program structure is carefully reconstructed to reduce instruction cache misses, which heavily degrade the processor performance. Preload instructions are used to load data to the data cache in parallel with successive instruction execution. Consequently, the cache miss penalties are drastically reduced. The current version of the software MPEG1 video encoder on the 200 MHz V830R/AV processor encodes SIF (352/spl times/240 pels) video at 30 frames/s with I, P and B picture types in 193 M clocks/s.

Conventional cache optimizations are usually confined to hardware. However, software optimizations are more flexible and allow faster hardware due to reduced complexity. The authors describe a method of using direct mapped caches more effectively by adapting program behavior. They introduce coarse-grained code reorganization as a software method of improving instruction cache hit rates. Based on trace analysis, cache conflicts are computed taking into account both temporal and spatial program locality. This leads to a precise prediction of cache behavior which is used to reorganize the code in address space. The potential of the solution is demonstrated by applying the code reorganizer to a variety of SPEC benchmarks. Both simulated and measured results are presented for various cache sizes. The results show significant performance gains across the various SPEC programs evaluated. >

Most schedulability analysis techniques for multi-core architectures assume a single worst-case execution time (WCET) per task, which is valid in all execution conditions. This assumption is too pessimistic for parallel applications running on multi-core architectures with local instruction or data caches, for which the WCET of a task depends on the cache contents at the beginning of its execution, itself depending on the tasks that were executed immediately before the task under study. In this paper, we propose two scheduling techniques for multi-core architectures equipped with local instruction and data caches. The two techniques schedule a parallel application modeled as a task graph, and generate a static partitioned non-preemptive schedule, that takes benefit of cache reuse between pairs of consecutive tasks. We propose an exact method, using an integer linear programming formulation, as well as a heuristic method based on list scheduling. The efficiency of the techniques is demonstrated through an implementation of these cache-conscious schedules on a real multi-core hardware: a 16-core cluster of the Kalray MPPA-256, Andey generation. We point out implementation issues that arise when implementing the schedules on this particular platform. In addition, we propose strategies to adapt the schedules to the identified implementation factors. An experimental evaluation reveals that our proposed scheduling methods significantly reduce the length of schedules as compared to cache-agnostic scheduling methods. Furthermore, our experiments show that among the identified implementation factors, shared bus contention has the most impact.

Migration-aware slot-based memory request scheduler to guarantee QoS in DRAM-PCM hybrid memories

We consider IPsec as a means to provide security for a bare (OS-less) PC in a networked environment. We first present the underlying bare computing architecture that includes IPsec components. We then describe our design and implementation of IPsec with ESP and IKEv2 support for a bare PC. Bare PC optimizations that provide higher efficiency include application and protocol intertwining, and minimization of inter-layer communication and data copying. We also evaluate IPsec performance on a bare PC and compare it with a similar Linux system. Our experimental results indicate that 1) the cost of ESP processing is approximately 6% more for incoming versus outgoing packets; 2) an approximately linear relationship between ESP processing time and packet size exists for both tunnel and transport modes; 3) ICMP and HTTP response times with IPsec are less on a bare PC than on a Linux system. In this paper, we consider the design and implementation of IPsec on a bare PC and evaluate its performance. We also provide some performance comparison with applications that run on Linux. Due to the novel characteristics of bare machine computing and its unique architecture, the design and implementation of IPsec for an AO is different from a conventional implementation of IPsec in an OS-based system. IPsec can be efficiently implemented on a bare PC by using optimizations not easily achieved in conventional systems. Examples are intertwining the application with network protocols within an AO, minimizing the cost of inter-layer communication, and eliminating data copying between application and network buffers. The main contributions of this research are: 1) an implementation of IPsec for a bare (OS-less) PC; 2) experimental results related to the cost of IPsec processing on a bare PC; and 3) experimental results related to the increase in response time of applications when IPsec is present for a bare PC and for a conventional OS-based (Linux) PC. These results can serve as a baseline for designing future versions of IPsec for high-performance or high-security applications and security gateways running on bare machines.

Resource Aware Placement of Data Analytics Platform in Fog Computing

Consistent low response time is essential for e-commerce due to intense competitive pressure. However, practitioners of web applications have often encountered the long-tail response time problem in cloud data centers as the system utilization reaches moderate levels (e.g., 50%). Our fine-grained measurements of an open source n-tier benchmark application (RUBBoS) show such long response times are often caused by Cross-tier Queue Overflow (CTQO). Our experiments reveal the CTQO is primarily created by the synchronous nature of RPC-style call/response inter-tier communications, which create strong inter-tier dependencies due to the request processing chain of classic n-tier applications composed of synchronous RPC/thread-based servers. We remove gradually the dependencies in n-tier applications by replacing the classic synchronous servers (e.g., Apache, Tomcat, and MySQL) with their corresponding event-driven asynchronous version (e.g., Nginx, XTomcat, and XMySQL) one-by-one. Our measurements with two application scenarios (virtual machine co-location and background monitoring interference) show that replacing a subset of asynchronous servers will shift the CTQO, without significant improvements in long-tail response time. Only when all the servers become asynchronous the CTQO is resolved. In synchronous n-tier applications, long-tail response times resulting from CTQO arise at utilization as low as 43%. On the other hand, the completely asynchronous n-tier system can disrupt CTQO and remove the long tail latency at utilization as high as 83%.

Optimizing security and quality of service in a real-time operating system using multi-objective Bat algorithm

In this paper, we investigate how the presence of a general purpose operating system influences the reliability of modern embedded Systems-on-Chips (SoCs). We experimentally study the difference in the neutron-induced error rate of SoCs when executing the application bare to the metal (i.e., without an underlying operating system) and on top of the Linux kernel. Our analysis demonstrates that Linux presence barely affects the Silent Data Corruption (SDC) rate whereas it greatly increases the system Functional Interruption (SEFI) rate (up to 7.48 times) if no preventive measures are taken. Nevertheless, we experimentally demonstrate that cache conflicts between the operating system and application can be leveraged to significantly reduce the Linux-induced SEFI rate increase. Moreover, we evaluate the OS software stack masking effect and show that the higher the abstraction layer in which an application is implemented, the lower its SDC rate. Furthermore, we analyze system reliability taking into account not only the resulting failure rates, but also the execution (and, thus, exposure) times.

Article Free Access Share on The impact of architectural trends on operating system performance Authors: M. Rosenblum Computer Systems Laboratory, Stanford University, Stanford CA Computer Systems Laboratory, Stanford University, Stanford CAView Profile , E. Bugnion Computer Systems Laboratory, Stanford University, Stanford CA Computer Systems Laboratory, Stanford University, Stanford CAView Profile , S. A. Herrod Computer Systems Laboratory, Stanford University, Stanford CA Computer Systems Laboratory, Stanford University, Stanford CAView Profile , E. Witchel Computer Systems Laboratory, Stanford University, Stanford CA Computer Systems Laboratory, Stanford University, Stanford CAView Profile , A. Gupta Computer Systems Laboratory, Stanford University, Stanford CA Computer Systems Laboratory, Stanford University, Stanford CAView Profile Authors Info & Claims SOSP '95: Proceedings of the fifteenth ACM symposium on Operating systems principlesDecember 1995Pages 285–298https://doi.org/10.1145/224056.224078Published:03 December 1995Publication History 188citation2,012DownloadsMetricsTotal Citations188Total Downloads2,012Last 12 Months295Last 6 weeks50 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF