Application of Indium Sheet Thermal Interface Material in Advanced Semiconductor Packaging

Vitrimeric phase change material facilitating 3D-structured boron nitride network for reliable thermal conductive interface materials

Thermal interface materials (TIMs) play a key role in the thermal management of microelectronic devices by providing a path of low thermal impedance between heat generating devices and heat dissipating components (heat spreader/sink). In addition, TIMs often provide mechanical coupling between the silicon device and the heat spreader/sink. During device operation, the adhesive joint between the heat generating device and heat spreader/sink is subjected to thermomechanical stresses due to differences in thermal expansion coefficients of the silicon device and the heat spreader material. The adhesive joint can consequently delaminate or debond from the mating surfaces causing a significant increase in thermal impedance across the thermal interface material. Hence, a TIM needs to offer improved thermal performance as well as enhanced reliability. In addition to these characteristics, several other requirements such as adhesion strength, response to different assembly parameters, and volatile content need to be considered and addressed during the development of a TIM. This paper discusses the development of such an interface material and a comprehensive performance evaluation of the new TIM.

Microstructure design and analysis of thermal interface materials using high heat- resistance natural fibers

The development of high power and compact size semiconductor packages lead to the challenge in the need of high thermal dissipation design. For package level thermal solution, metal (especially copper) heat spreader and metal/metal-oxide filler thermal interface material are widely adopted. However, the thermal performance of packages is limited by isotropic conductive behavior of most of these materials. The thermal conducting performance could be further improved by directing the heat transportation in the direction desired, for instances the in-plane dissipation for heat spreader and the out-of-plane dissipation for thermal interface material. This present study reported the successful adoption of anisotropic thermal conductive pyrolytic graphite sheet as heat spreader and vertically aligned graphite sheet as thermal interface material in semiconductor package, individually. The Joint Electron Device Engineering Council standard still air junction to ambient measurement experiment shows that a flip chip ball grid array package incorporated with a pyrolytic graphite sheet as heat spreader improved thermal resistance of the module by 20%. The thermal dissipation behavior of the module was simulated with a well validated computational thermal dynamics model based on the experimental results. The anisotropic thermal conductive vertically aligned graphite sheet was also adopted as thermal interface material to replace the nowadays grease type thermal interface material. A thermal test chip assembled large size high performance flip chip ball grid array package mounted on a Joint Electron Device Engineering Council defined 4 layers thermal test printed circuit board was chosen as the test vehicle for thermal interface material performance test. The junction to case measurement experiment shows that the package with the anisotropic conductive thermal interface material improved the thermal resistance by 40%. Some novel designs were proposed basing on the application of this anisotropic thermal conductive material as validated by thermal simulation study. Package design guideline basing on the implementation of the anisotropic thermal conductive material will be discussed in this paper.

Historically, for semiconductors subject to standard operating temperatures--which tend not to exceed 125°C--the Tg (glass transition temperatures) of the organic packaging materials protecting the chips is usually around 175°C. Given that, when it comes to electronics operating at high temperatures—typically an environment where the ambient temperature exceeds 200°C—the use of organic materials is generally prohibited due to rapid degradation. At those elevated temperatures, the packaging materials selected are generally composed of metals and ceramics but these materials come with their own shortfalls as well as higher material and manufacturing costs. Therefore, it would be desirable if there were ‘ruggedized’ versions of the organic compounds so commonly used in semiconductor packaging but available for more extreme temperatures, both to reduce cost and package footprint. Meanwhile, the demands from recent developments in high performance computing (HPC) and high-speed data networks means a greater need for increased power and thermal dissipation coupled with very large package body sizes to accommodate the high I/O count. The latest in server microprocessor (MPU) products can easily generate up to 300W during operation, and the heat generated must be quickly transported away from chip to prevent the threat of thermal shutdown. The thermal dissipation issue is controlled by the use of heat spreaders and heat sinks, both of which are intended to make contact with the back-side of a flipped MPU via a thermal interface material (TIM), as part of a large die, large body-size flip-chip ball grid array (FCBGA) package. The thermal interface materials discussed here are examples of organic engineered materials that are capable of withstanding higher operating temperatures than typically seen by semiconductors encased in organic-based packaging. This paper will look at the key material and mechanical attributes for a good thermal interface material, examines the pros-and-cons of various thermal interface material formulations, and discusses the factors for reliable thermal dissipation performance.

Power dissipation in electronic devices is projected to increase significantly over the next ten years to the range of 50-150 Watts per cm2 for high performance applications [1]. This increase in power represents a major challenge to systems integration since the maximum device temperature needs to be around 100 C. One of the primary obstacles to the thermal management of devices operating at such high powers is the thermal resistance between the device and the heat spreader or heat sink that it is attached to. Typically the in situ thermal conductivity of interface materials is in the range of 1 to 4 W/mK, even though the bulk thermal conductivity of the material may be significantly higher. In order to improve the effective in-situ thermal conductivity of interface materials nanotubes are being considered as a possible addition to such interfaces. The primary approach taken in the current study is to analyze the enhancement of the thermal interface by adding carbon nano tubular cylinders that are oriented in the direction of transport. This paper presents the results of an analytical study of transport in a thermal interface material that is enhanced with carbon nanotubes. A variety of parametric analyses are carried out, such as by varying the inner diameter of the nanotube and the power dissipation, and the effect on spreading resistance is calculated. The results indicate that for high thermal conductivity nanotubes there is a significant increase in the effective thermal conductivity of the thermal interface material.

Thermal management of device level packaging continues to present many technical challenges. In the typical chip heat sink assembly, the highest resistance to heat flow comes from the thermal interface material (TIM). The thermal conductivities of TIMs remain in the range of 1-4 W/mK due to the properties and structure of small dispersed solids in polymer matrices. As a result of the rising design power and heat flux at the silicon die, new ways to improve the effective in situ thermal conductivity of interface materials are required. This paper will introduce a unique TIM enhanced with ultrahigh density wafer level thin film compliant interconnects named smart three axis compliant (STAC) interconnects. The MEMS technology based STAC interconnect is directly fabricated onto a silicon wafer and embedded into the TIM to provide an enhanced conductive path between the die/package and the heat sink. Numerical and analytical analyses of the thermal conduction in the TIM embedded with STAC interconnects are performed. The objective of the study is to provide comprehensive design strategies for effective implementation of this type of TIM for specific applications. Parametric studies are conducted to examine the thermal conductivity of the microinterconnect enhanced TIM for varying materials, configurations, and geometry of the microinterconnects. For the modeling, a periodic element model of chip-TIM configuration with top heat sink is developed and maximum temperatures are determined in order to evaluate the conductive effect of the microinterconnect. In addition, an investigation of the conductive transport in a more complicated chip stack is considered. A 3-D thermal analysis is conducted for a multi-chip stack package with and without through-silicon-vias. The numerical results show that the microinterconnects significantly improve the thermal performance of the TIM. Finally, further steps toward achieving a chip-level design optimization and fabrication process using microinterconnects structured TIM is proposed.

In a flip chip BGA package, thermal interface materials (TIMs) are applied for thermal management between the die and the heat spreader or between the heat spreader and the heat sink to conduct the heat generated in the die during component operation. Without a thermal interface, the die will overheat and the components will not function properly. Advanced microelectronics packaging demands high and dynamic standards of its supplier industries in relation to speed, precision and flexibility. For example, the demands on functionality, power density and performance of the components within a die are largely enhanced along with TIM requirements for higher heat resistance. Manufacturers are being asked to apply TIMs on more dies in more complicated geometries and to dispense them during any packaging process. This brings increased challenges for TIM dispensing equipment, such as the ability to handle abrasive and dry TIMs at a high throughput while maintaining precision and repeatability. A high-precision, high-throughput TIM dispensing process has been developed to fill the gap between the traditional slower dispensing of simple patterns and the challenges from emerging package designs. This process is being used in flip chip BGA production lines in package applications from consumer electronics to automotive products. These production lines are in full 24/7 operation with each dispensing system running at 240 units per hour (uph) for audio-video consumer electronics, 360 uph for CPUs/GPUs on smart phones and 750 uph for automobile control panels and computation servers. In this new dispensing system, the valve can be tightly controlled to achieve high dispensing accuracy at fast speeds. The dispense pattern and route can be modified at no cost, in minutes, and during any step in the design or the assembly stage. Shapes that can be dispensed include dots, lines, boxes and circles with fine height and edge definitions of 25micron and 45micron. The process can cover a wide range of pattern dimensions between 0.5mm and 100mm at flow rates of 30–370 mg/sec at a repeatability of 3–15% three sigma. Even TIM that has viscosity as high as 1500kcPs with a heavy load of large and coarse particles such as metals, ceramic and glass beads can be dispensed using this equipment and process. New equipment and processes are under development to further push the limit on higher throughput and precision, increased flexibility and material dispensability.

A thermal solution for an array of voltage transformer modules which are cooled by a large area, common aluminum heat spreader for a high end server was evaluated using an in situ, capacitive bond line thermal measurement technique. The method measures the capacitance of a non-electrically conducting thermal interface material (TIM) between the electronic module and heat spreader to quantify the TIM bond line effective thickness during assembly and operation. The thermal resistance of the TIM has the same geometric dependence as the inverse of capacitance, therefore, the capacitive technique also provided a monitor of the thermal performance of the interface. This technique was applied to measure the bond line in real time during the assembly of the heat spreader to an array of 37 modules mounted on a printed circuit board. The results showed that the target bond lines were not achieved by application of a constant force alone on the heat spreader, and guided an improved assembly process. The mechanical motion of the TIM was monitored in situ during thermal cycling and found to fluctuate systematically from the hot to cold portions of the thermal cycle, either compressing or stretching the TIM respectively. The capacitive bond line trend showed thermal interface degradation vs. cycle count for several modules which was confirmed by disassembly and visual inspection. Areas of depleted TIM ranged as high as 25% of the module area. Several design and material changes were shown to improve the TIM stability. Power cycling tests were run in parallel to the thermal cycle tests to help relate the results to field performance. The capacitance technique enabled the development and verification of a thermal solution for a complex mechanical system early in the development cycle.

The thermal electric cooler (TEC) is a solid state heat pump and is a fundamental building block of liquid-cooled thermal tools used for temperature margining in platform validation systems. TECs are prone to cracking and thermal performance degradation during power cycling similar to those in flip-chip packages. A modeling methodology is developed to enable analysis of the thermal tool and understand better the stresses and deformations that the TEC go through during power cycling. TEC cracking and performance degradation have been perennial issues for liquid-cooled thermal tools. Prior method to deal with TEC reliability issues for thermal margining tools deployed in the field was to rework the thermal tools by refreshing the TECs. This is costly and time-consuming process and has a direct impact on the time to market of the silicon. In this paper, we introduce a combined computational fluid dynamics and finite element modeling techniques to explain the reliability issues observed in the TEC. This novel modeling methodology offers a physics-based analysis of the inner mechanics of the thermal margining tool. This paper focuses on a typical liquid-cooled thermal tool and uses experimental data to validate the model. The study also uses the model to do sensitivity analysis on Thermal Interface Material (TIM), fastening, and material properties. This technique can be used to reduce thermal stresses in the TEC, predict the performance of future thermal tool designs, optimize the performance of thermal tools, and extend their useful life while reducing the amount of reliability testing necessary during development. This is especially critical as the number and variety of thermal tools proliferate. This method can serve as a best known method (BKM) for future liquid-cooled thermal tool designs.

Thermal interface materials (TIMs) play a critical role in enhancing the efficiency of next-generation packaging technologies within the semiconductor industry.[1] The increasing heat density in the latest transistor node sizes, coupled with the continuous increase in die sizes, presents a significant challenge for TIM1s. Modern TIM1s used in semiconductor packaging must not only offer remarkably low thermal resistances (<5 mm^2·K/W), but also exhibit exceptional mechanical performance to accommodate the significant warpage resulting from coefficient of thermal expansion (CTE) mismatches in the packages. Recently, researchers have proposed the use of liquid metal embedded elastomers (LMEEs) [2] as thermal interface materials [3] to create a TIM based on LMEEs that can meet the demands of the most challenging applications. In this presentation, we offer material-level characterization and thermal test vehicle (TTV) testing of LMEEs. Our findings demonstrate that achieving an ultra-thin bondline thickness on the order of 20 µm allows us to attain an exceptionally low thermal resistance of less than 5 mm^2·K/W between the die and integrated heat spreader (IHS). Furthermore, we provide insights into the interplay between adhesion, stretchability, and modulus of the TIM. These are crucial factors for ensuring the TIM has the necessary mechanical properties to maintain the integrity of the interface between the die and the heat sink, thus preventing any degradation in thermal resistance following thermal shock tests. In the end, we present data on the in-situ changes in thermal resistance of LMEEs as a function of strain while cured between two silicon dies, shedding light on the thermomechanical behavior of LMEEs.

Semi-in-situ thermal transport characterization of thermal interface materials through a low-frequency thermoreflectance technique

A variety of thermal interface materials (TIMs) were investigated to find a suitable TIM for improving the performance of thermoelectric power generators (TEGs) operating in the medium-temperature range (600–900 K). The thermal resistance at the thermal interface between which the TIM was inserted was evaluated. The TIMs were chosen on the basis of their thermal stability when used with TEGs operating at medium temperatures, their electrical insulating properties, their thermal conductivity, and their thickness. The results suggest that the boron nitride (BN)-based ceramic coating, Whity Paint, and the polyurethane-based sheet, TSU700-H, are suitable TIMs for the heat source and heat sink sides, respectively, of the TEG. Use of these effectively enhances TEG performance because they reduce the thermal contact resistance at the thermal interface.

Its self-heating process directly affects the optical performance and reliability of light – emitting diodes (LEDs). It is important to disperse the generated heat from LED to surrounding atmosphere and keep the LED light performances same as declared by the manufacturer. Thermal interface material (TIM) is applied in between sink and source to reduce contact resistance at the junction between substrate and heat sink interface of the LED modules. This paper provides an assessment on ‘thermal interface materials’. Here different TIM materials used and the performance and problems of these commercial interface materials are discussed. From this study, one can calculate the temperature distribution in the sink area for different types of TIM materials under thermal conductivity perspective and be able to find the capability of dissipation of heat at the end surfaces of heat sinks, and design their system as well. In another process, TIMs with different thickness and input drive currents for the COB-based LED are investigated by using COMSOL simulation software. The results show that the junction temperature of the LED luminaire increases and reduce the lifetime when the input drive current and thickness of the TIM layers increase.

Heat transfer performance of a compact heat exchanger based on metal foam and Thermal Interface Material (TIM)