Application Specific Instruction Accelerator for Multistandard Viterbi and Turbo Decoding

Flexible baseband receivers gain the interest of many research efforts to enable the design of future multi-modes multistandards terminals. A main challenge in this domain is to provide this flexibility with minimum overhead in terms of area, speed, and energy. In this regard, heterogeneous multiprocessor platforms are emerging as a promising implementation solution. However, the heterogeneity of such platforms makes it complex to find the required number of processors supporting a specific configuration (i.e. requirements level). This paper investigates, in this context, the significant optimization potential both at design-time and at run-time regarding the selection of the most appropriate hardware configuration of a multiprocessor platform for iterative demapping and channel decoding. A formal representation of the architectural solution space which allows designers to find the minimum hardware configuration is proposed. The proposed approach is illustrated through a flexible multi-ASIP hardware platform for iterative demapping and channel decoding.

SUMMARYIn wireless communication, Viterbi decoding algorithm (VDA) is the one of most popular channel decoding algorithms, which is widely used in WLAN, WiMAX, or 3G communications. However, the throughput of Viterbi decoder is constrained by the convolutional characteristic. Recently, the three‐point VDA (TVDA) was proposed to solve this problem. In TVDA, the whole procedure can be divided into three phases, the forward, trace‐back, and decoding phases. In this paper, we analyze the parallelism of TVDA and propose parallel TVDA on the multi‐core CPU, graphics processing unit (GPU), and field programmable gate array (FPGA). We demonstrate approaches that fully exploit its performance potential on CPU, GPU, and FPGA computing platforms. For CPU platforms, we perform two optimization methods, single instruction multiple data and multithreading to gain over 145 × speedup over the naive CPU version on a quad‐core CPU platform. For GPU platforms, we propose the combination of cached memory optimization, coalesced global memory accesses, codeword packing scheme, and asynchronous data transition, achieving the throughput of 404.65 Mbps and 12 × speedup over initial GPU versions on an NVIDIA GeForce GTX580 card and 7 × speedup over Intel quad‐core CPU i5‐2300, under the same manufacturing year and both with fully optimized schemes. In addition, for FPGA platforms, we customize a radix‐4 pipelined architecture for the TVDA in a 45‐nm FPGA chip from Xilinx (XC6VLX760). Under 209.15‐MHz clock rate, it achieves a throughput of 418.30 Mbps. Finally, we also discuss the performance evaluation and efficiency comparison of different flexible architectures for real‐time Viterbi decoding in terms of the decoding throughput, power consumption, optimization schemes, programming costs, and price costs.Copyright © 2013 John Wiley & Sons, Ltd.

As the promising novel multiple access scheme for the 5th generation (5G) wireless communication system, pattern division multiple access (PDMA) technology can improve the spectral efficiency and support the massive connection based on the reasonable unequal diversity between users. Compared with traditional multiple access technologies, PDMA brings more serious multiple address interference to hinder the multiuser detection. The universal detection algorithm with low complexity and high performance is one of the main challenges of PDMA technology. In this paper, we proposed a new iterative detection and decoding algorithm, which is a successive interference cancellation (SIC) iterative processing based on the minimum mean square error (MMSE) detection and channel decoding algorithm. It is essentially a SIC iterative processing based on some users' information has been correctly decoded by the MMSE detection and the channel decoder. The proposed multiuser detection algorithm can prevent the error propagation by the cyclic redundancy check (CRC). The simulation results show that the proposed algorithm can get significant performance gains over traditional multiuser detection algorithms.

Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications.It provides an alternative approach to block codes for transmission over a noisy channel.The block codes can be applied only for the block of data.The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder.Power reduction in Viterbi decoder could be achieved by reducing the number of states.A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed.Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN).It operates on data stream and has memory that uses previous bits to encode.The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code.The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register.A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems.It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.The Viterbi decoder of Constraint length 7 and code rate ½ is considered.The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

The Viterbi algorithm (VA) is the maximum likelihood decoding algorithm for convolutionally encoded data. Improvements in the performance of a concatenated coding system that uses VA decoding (inner decoder) can be obtained when, in addition to the standard VA output, an indicator of the reliability of the VA decision is delivered to the outer stage of processing. Two different approaches of extending the VA are considered. In the first approach, the VA is extended with a soft output (SOVA) unit that calculates reliability values for each of the decoded output information symbols. In the second approach, coding gains are obtained by delivering a list of the L best estimates of the transmitted data sequence, namely the list Viterbi decoding algorithm (LVA). Our main interest is to evaluate the LVA and the SOVA in comparison with each other, determine suitable applications for both algorithms and to construct extended versions of the LVA and the SOVA with low complexity that perform the task of the other algorithm. We define a list output VA using the output symbol reliability information of the SOVA to generate a list of size L and that also has a lower complexity than the regular LVA for a long list size. We evaluate the list-SOVA in comparison to the LVA. Further, we introduce a low complexity soft symbol output viterbi algorithm that accepts the (short) list output of the LVA and calculates for each of the decoded information bits a reliability value. The complexity and the performance of the soft-LVA (LVA and soft decoding unit) is a function of the list size L. The performance of the soft-LVA and the SOVA are compared in a concatenated coding system. A new software implementation of the iterative serial version of the LVA is also included. >

Four-Dimensional 8PSK Trellis-Coded Modulation (4D-8PSK-TCM) is recommended as an efficient coded modulation standard for the Earth Exploration Satellite Service (EESS) 8025-8400 MHz band by the Consultative Committee for Space Data System (CCSDS). The advantage of 4D-8PSK-TCM is that coding gains can be achieved without expanding the bandwidth relative to the un-coded signal set. In this paper, the 4D-8PSK-TCM system with the modulation efficiency of 2.5 bit/symbol and its Viterbi decoding are presented and the Viterbi decoding algorithm is implemented on Matlab Simulink. During the algorithm implementation, an auxiliary trellis is introduced to reduce greatly the number of computations of metrics of each path. In this way, there are only 64 comparisons to compute the metrics in comparing with the 2032 comparisons required in a directly computing approach.

Rapidly growing demand for high data rates in wireless communication systems is the cause of the merging of Multiple Input Multiple Output (MIMO) and Orthogonal Frequency Division Multiplexing (OFDM) techniques. MIMO-OFDM technique needs Radio Frequency (RF) front end in each antenna, which is not effective for large dimensional antenna size. Therefore, RF front end on the receiver side will be simplified using a single RF technique based on the Electrically Steerable Parasitic Array Radiator (ESPAR) antenna. In real life, a channel cannot be ideal. Therefore, before the signal is transmitted, that signal must be coded to minimized errors when the data transmission process. Convolutional code is a coding technique that can detect and correct error bit (error control coding) and that it is expected to reduce the quantity of Bit Error Rate (BER). In this research, a simulation is designed to analyze single RF performance on the MIMO-OFDM system using Vertical Bell Laboratories Space-Time (VBLAST) detection for convolutional code encoder and Viterbi decoder. The result simulation shows that the channel estimation technique works well on the MIMO-OFDM system using single RF, which is shown in the magnitude and phase curves against the subcarrier index between the theory channel and the estimated channel are at almost the same points. VBLAST-ZF detector performance is shown in the BER curve against SNR, where the difference BER value for SNR value 10 dB between the theory channel and the estimated channel is 0.001499. Channel coding technique using convolutional code encoder and Viterbi decoder with a rate of ½ works well on the MIMO-OFDM system using single RF which is shown in the BER curve against SNR, where BER value with coding technique is smaller than BER value without coding technique.

A new class of convolutional codes, called skew convolutional codes, that extends the class of classical fixed convolutional codes, is proposed. Skew convolutional codes can be represented as periodic time-varying convolutional codes but have a description as compact as fixed convolutional codes. Designs of generator and parity check matrices, encoders, and code trellises for skew convolutional codes and their duals are shown. For memoryless channels, one can apply Viterbi or BCJR decoding algorithms, or a dualized BCJR algorithm, to decode skew convolutional codes.

To meet the goal of tenfold increase in spectral efficiency, interference cancellation and multiuser detection are expected to be important tasks of fifth-generation (5G) radio access systems. Both tasks can be realized by joint detection algorithms. However, joint detection algorithms such as maximum likelihood (ML) detection have a high computational complexity. Previous works have shown that joint detectors based on Markov chain Monte Carlo (MCMC) methods can achieve similar results compared to ML detection with a large reduction in the computational complexity for systems with a large number of streams or users. The purpose of this work is to present a MIMO joint detector based on MCMC methods and evaluate it within the constraints of LTE Advanced (LTE-A), namely, using at most 8 transmit antennas and 64-QAM modulation. The evaluation is done separately from the channel decoder. Moreover, the complexity of the presented algorithm is compared to the one of an ML detector. The results show that the proposed MIMO detector offers a similar detection error rate compared to an ML detector. Furthermore, it was observed that the complexity reduction is significant for systems with more than six transmit antennas.

The major applications of multiprocessor system-on-a-chip (SoC) comprises of heterogeneous processors on a single chip. In this kind of integration, major problem is the cache coherence problem i.e. Maintenance of data integrity. In this paper, we propose a record based methodology to remove the cache coherence problem in heterogeneous multiprocessor platforms with shared and private memories. As shown in our simulation results, a performance improvement up to 18.75% is achieved while using proposed approach in four different benchmarks on LIMES simulator as compared to three other snoopy cache coherence protocols Dragon, Berkeley and MESI.

Heterogeneous multi-processor platforms are becoming widely diffused in the embedded system domain, mainly because of the opportunity to improve timing performance and, at the same time, to minimize energy/power consumption and costs. In using such kind of platforms, to be able to consider the trade-offs among different goals, a Design Space Exploration (DSE) is generally adopted. For this, existing DSE approaches typically rely on evolutionary algorithms to solve Multi-Objective Optimization Problems (MOOP) by minimizing a linear combination of weighted objective functions (i.e., Weighted Sum Method, WSM). The problem is then shifted towards the identification of weights able to represent desired trade-offs. In such a context, this paper focuses on DSE for heterogeneous multi-processor embedded systems and introduces an approach that, while still driven by a decision maker, is able to self-tune weights to equalize objective functions contribution. In particular, this work presents a self-equalized WSM integrated into a genetic algorithm used to identify sub-optimal implementation alternatives in the context of an Electronic System Level HW/SW Co-Design flow.

The paper investigates the influence of Dynamic Voltage Frequency Scaling for bi-objective (makespan and energy consumption) Directed Acyclic task Graph scheduling on heterogeneous multi-processor platform. The proposed resolution method of solving conflicting criteria relies on Multi-Objective Evolutionary Algorithms. Two voltage frequency approaches are compared: one using only 2 levels (minimal and maximal) and the other one using a larger number. The approaches are benchmarked on applications with Laplace transformation and Gaussian elimination structures using the NSGAII algorithm. The results show that while the Two-level approach generates more discriminated solutions on the Pareto front, the solutions are of a lower quality than in the Multi-level approach.

Energy efficient task partitioning and real-time scheduling on heterogeneous multiprocessor platforms with QoS requirements

Mapping a dataflow application onto a heterogeneous multiprocessor platform cannot longer be static. It has to adapt dynamically depending on the data and on the communication between the computation cores. This is typically the case for mobile devices that run multimedia applications. This paper presents an algorithm fast enough to be executed at run-time. In addition to computation cost, our approach relies on a communication model to estimate the delay for transmitting data. The algorithm is compared with METIS tool for random dataflow graphs and two video decoders, MPEG4-SP and HEVC, considering heterogeneous multiprocessor platforms composed of 4 to 8 processors and 6 accelerators. Results on a Zynq platform show that our algorithm is about 40x faster than METIS tool for the same throughput (frames per second) on a platform with 8 processors and 6 accelerators.

The problem of partitioning systems of independent constrained-deadline sporadic tasks upon heterogeneous multiprocessor platforms is considered. Several different integer linear program (ILP) formulations of this problem, offering different tradeoffs between effectiveness (as quantified by speedup bound) and running time efficiency, are presented.