Communication-model based embedded mapping of dataflow actors on heterogeneous MPSoC

Considering the evolution towards highly variable data flow applications based on an increasing impact of dynamic actors, we must target at runtime the best matching between dataflow graphs and heterogeneous multiprocessor platforms. Thus the mapping must be dynamically adapted depending on data and on communication loads between the computation cores. This is typically the case for mobile devices that run multimedia applications. The problem of mapping a dataflow application, e.g. a network of computational actors, on a multiprocessor platform can be modeled as a problem of partitioning where the cells are the dataflow actors and the partitions are the processors. While the benefit of executing a computational part by one processor rather than another one is usually well shown, the migration overhead is also usually not considered. This paper presents a dynamic mapping algorithm that is performed at runtime, based on a single-move possibility that jointly considers the cost and benefit of possible migrations. The method is first applied on a set of randomly generated benchmarks with different features and different scenarios. Then it is applied to a MPEG4 simple profile video decoder with different input sequences. The results systematically show that the runtime mapping significantly improves the initial mapping. It is fast enough to be executed at runtime in order to track the best mapping according to data variations. The other observation is that not considering the migration cost of the new mapping could lead to worst performance than the original one.

Flexible baseband receivers gain the interest of many research efforts to enable the design of future multi-modes multistandards terminals. A main challenge in this domain is to provide this flexibility with minimum overhead in terms of area, speed, and energy. In this regard, heterogeneous multiprocessor platforms are emerging as a promising implementation solution. However, the heterogeneity of such platforms makes it complex to find the required number of processors supporting a specific configuration (i.e. requirements level). This paper investigates, in this context, the significant optimization potential both at design-time and at run-time regarding the selection of the most appropriate hardware configuration of a multiprocessor platform for iterative demapping and channel decoding. A formal representation of the architectural solution space which allows designers to find the minimum hardware configuration is proposed. The proposed approach is illustrated through a flexible multi-ASIP hardware platform for iterative demapping and channel decoding.

This article presents the design of a video decoder using dynamic task partition approach on a heterogeneous dual-core embedded platform. For such systems, static task partition between the two cores at design time is a typical approach for application development. In this article, we propose a runtime dynamic task partition model and implement an MPEG-4 Simple Profile video decoder using this approach on a TI OMAP 5912 platform. Comparing with a traditional mobile video decoder optimized for the same DSP core, the performance gain from dynamic task partition is 38.4% on average. More importantly, the gain is achieved with the design constraint that the implementation effort for the dynamic task partition decoder is about the same as the effort using design-time task partition model. Unlike common belief that the inter-processor communication overhead would be too high to justify intense cooperation between two heterogeneous cores, this paper shows that it is indeed beneficial to adopt dynamic task partition model on commercially available heterogeneous multi-core platforms.

The major applications of multiprocessor system-on-a-chip (SoC) comprises of heterogeneous processors on a single chip. In this kind of integration, major problem is the cache coherence problem i.e. Maintenance of data integrity. In this paper, we propose a record based methodology to remove the cache coherence problem in heterogeneous multiprocessor platforms with shared and private memories. As shown in our simulation results, a performance improvement up to 18.75% is achieved while using proposed approach in four different benchmarks on LIMES simulator as compared to three other snoopy cache coherence protocols Dragon, Berkeley and MESI.

Heterogeneous multi-processor platforms are becoming widely diffused in the embedded system domain, mainly because of the opportunity to improve timing performance and, at the same time, to minimize energy/power consumption and costs. In using such kind of platforms, to be able to consider the trade-offs among different goals, a Design Space Exploration (DSE) is generally adopted. For this, existing DSE approaches typically rely on evolutionary algorithms to solve Multi-Objective Optimization Problems (MOOP) by minimizing a linear combination of weighted objective functions (i.e., Weighted Sum Method, WSM). The problem is then shifted towards the identification of weights able to represent desired trade-offs. In such a context, this paper focuses on DSE for heterogeneous multi-processor embedded systems and introduces an approach that, while still driven by a decision maker, is able to self-tune weights to equalize objective functions contribution. In particular, this work presents a self-equalized WSM integrated into a genetic algorithm used to identify sub-optimal implementation alternatives in the context of an Electronic System Level HW/SW Co-Design flow.

The paper investigates the influence of Dynamic Voltage Frequency Scaling for bi-objective (makespan and energy consumption) Directed Acyclic task Graph scheduling on heterogeneous multi-processor platform. The proposed resolution method of solving conflicting criteria relies on Multi-Objective Evolutionary Algorithms. Two voltage frequency approaches are compared: one using only 2 levels (minimal and maximal) and the other one using a larger number. The approaches are benchmarked on applications with Laplace transformation and Gaussian elimination structures using the NSGAII algorithm. The results show that while the Two-level approach generates more discriminated solutions on the Pareto front, the solutions are of a lower quality than in the Multi-level approach.

Energy efficient task partitioning and real-time scheduling on heterogeneous multiprocessor platforms with QoS requirements

The problem of partitioning systems of independent constrained-deadline sporadic tasks upon heterogeneous multiprocessor platforms is considered. Several different integer linear program (ILP) formulations of this problem, offering different tradeoffs between effectiveness (as quantified by speedup bound) and running time efficiency, are presented.

There is an increasing demand for converged solution for multi-standard radio processors to support existing and future standards. In this work, heterogeneous multi-processor platform is proposed for multi standard wireless communication system which is programmable and scalable in adapting to future standards. Channel decoding algorithms form important constituent of wireless communication system because of their computational complexity. A programmable radio processor is proposed for channel decoding with application specific instruction accelerators. Viterbi and Turbo channel decoding algorithms are analyzed for computational parallelism in the algorithms and for hardware reusability across the algorithms. Application specific instruction accelerator is designed by exploiting similar characteristics and computational parallelism across the algorithms. The analysis shows that the throughput of 54Mbps for UWB Viterbi Decoder and 12 Mbps for UMTS Turbo Decoder at 91.7MHz can be achieved using the proposed design.

Heterogeneous multiprocessor platforms are becoming widespread in the embedded system domain, mainly for the opportunity to improve timing performance and to minimize energy/power consumption and costs. Therefore, when using such platforms, it is important to adopt a Design Space Exploration (DSE) strategy that considers compromises among different objectives. Existing DSE approaches are generally based on evolutionary algorithms to solve Multi-Objective Optimization Problems (MOOPs) by minimizing a linear combination of weighted cost functions (i.e., Weighted Sum Method, WSM). In this way, the main issues are related to reduce timing execution while trying to improve the evolutionary algorithm performance, introducing strategies that attempt to bring better solutions. Code parallelization is one of the most used approaches in this field, but no standard methods have been released since different aspects could affect the performance. This approach leads to exploit parallel and distributed processing elements in order to implement evolutionary algorithms. In the latter case, if we consider genetic algorithms, it is possible to talk about Parallel Genetic Algorithms (PGA). Considering this context, this paper focuses on DSE for heterogeneous multi-processor embedded systems and introduces an improvement that reduces execution time using parallel programming languages (i.e., OpenMP) inside the main genetic algorithm approach, while trying to lead to better partitioning solutions. The descriptions of the adopted DSE activities and the OpenMP implementation, validated by means of a case study, represent the core of the paper.

In this work, we consider hard real-time applications scheduled upon heterogeneous multiprocessor platforms. The originality of this study is to consider multi-mode real-time applications (software aspects) and reconfigurable-heterogeneous hardware platforms (composed of CPUs, GPUs, FPGAs...). Our approach is based on a multi-mode protocol, for mode-dependent tasks upon reconfigurable hardware. The goal is to handle predictable switches between different task sets and different hardware settings. The novelty here is the dynamic hardware and software reconfigurability. First, we propose a formal model of the applications and reconfigurable hardware platforms. We then propose and prove correct a mode change protocol. We propose in particular a validity test for the verification of the timing constraints of the application --- including the time allowed to complete a mode change. We also perform a complete evaluation. We study the theoretical complexity of the protocol, use a simulation to evaluate the efficiency of our solution, and finally propose a competitive analysis of our protocol to prove that it is 2-competitive.

International audience

In recent years, the semiconductor industry has turned its focus towards heterogeneous multi-processor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility also perfectly supports the emerging market of interactive, mobile data and content services. The platform's performance and energy depend largely on how well the data-dominated services are mapped on the memory subsystem. A crucial aspect thereby is how efficient data is transferred between the different memory layers. Several compilation techniques have been developed to optimally use the available bandwidth. Unfortunately, they do not take the interaction between multiple threads running on the different processors into account, only locally optimize the bandwidth nor deal with the dynamic behavior of these applications. The contributions of this chapter are to outline the main limitations of current techniques and to introduce an approach for dealing with the dynamic multi-threaded of our application domain.

Given a collection of recurring tasks or processes that comprise a real-time system, and a collection of available processing units of different kinds upon which to execute them, the heterogeneous multiprocessor feasibility problem is concerned with determining whether the given tasks can be executed on the available processing units in such a manner that all timing constraints are met. A preemptive scheduling model is assumed. Under the partitioned scheduling paradigm - each task may execute on only one processor - this problem has previously been shown to be intractable. Under the global scheduling paradigm, however, a polynomial-time algorithm for heterogeneous multiprocessor feasibility analysis is presented here, and proved correct. An upper bound is derived upon the number of tasks that need to be executed upon multiple processors: even in the worst case, it is shown that this number is reasonable small (of the order of the number of processors), implying that the benefits of global scheduling are available without requiring that too many tasks be forced to execute on multiple processors.

With the emergence of inexpensive commercial off-the-shelf (COTS) parts, heterogeneous multi-processor HPC platforms have now become more affordable. However, the effort required in developing real-time applications that require high-performance and high input/output bandwidth for the HPC systems is still difficult. There are no software tools that allow an engineer to develop and field applications efficiently on the HPCs. This paper describes Honeywell's Multi-domain Embedded System Architect tool suite (MESA). The tool suite allows an engineer to rapidly develop an application on a COTS based heterogeneous HPC platform, effectively reducing the development time. To illustrate the cost benefit and the user friendliness of MESA, the mapping of the bistatic radar application on Honeywell's HPC will be presented.