Approximation of multiple constant multiplications using minimum look-up tables on FPGA

The multiple constant multiplication (MCM) block, which realizes the multiplication of constants by a variable, is a ubiquitous operation in digital signal processing (DSP) systems. It can be implemented using generic multipliers or shifts and adders/subtractors. This paper addresses the problem of finding the minimum number of adders/subtractors to realize the MCM block while a number of multipliers are available to realize some constant multiplications. Such a situation appears in the design of DSP systems on field programmable gate arrays (FPGAs) which also include generic multipliers. We present a 0-1 integer linear programming (ILP) formulation of this problem, yielding an exact common subexpression elimination (CSE) method. Due to the NP-completeness of this problem, we also introduce an approximate graph-based (GB) algorithm. Experimental results show that the proposed methods can find better solutions than a state-of-art algorithm and the use of different number of multipliers in the MCM block leads to filter designs with different number of slices, delay, and power dissipation which enable a designer to choose the one that fits best in an application.

A radio telescope analyzes radio frequency (RF) signal received from celestial objects. It consists of an antenna, a receiver, and a spectrometer. The spectrometer converts thetime domain signal into the frequency domain signal by an FFToperation. This paper proposes an FFT circuit based on nestedresidue number system (NRNS). Since the FFT operation is themost computationally intensive part, parallel implementation isnecessary to realize a high-speed FFT. We used an FPGA to implementthe circuit. The FPGA consists of look-up tables (LUTs) andblock RAMs (BRAMs). For direct parallel FFT realization usingan existing FPGA library, the number of LUTs for the complexmultipliers is the bottleneck. To reduce the number of LUTsin an FPGA, we increase the dynamic range stage by stage. Inthis case, NRNS2NRNS converters that convert smaller dynamicrange to larger dynamic range are necessary. We implementedthe proposed NRNS FFT on the Xilinx Corp. Virtex 7 FPGA. Compared with a conventional binary FFT, although the numberof block RAMs (BRAMs) was increased by 20.0-156.5%, in theRNS FFT, the number of LUTs was decreased by 42.4-47.8%and the maximum clock frequency was increased by 9.3-41.7%.With this technique, we successfully implemented an FFT thatsatisfied the required size and speed specifications on an availableFPGA, since the excessive number of LUTs was the bottleneckof the binary FFT.

Spike-based compact digital neuromorphic architecture for efficient implementation of high order FIR filters

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

10 - Hardware and software development tools

Energy consumption in Digital Signal Processing (DSP) application is a vital parameter of consideration. Mostly DSP applications deplete power. Battery constraint is important in many mobiles, processors, and sensor-related devices. The major critical operations in DSP architecture are multiplication and addition. Multiplication process is performed using repetitive addition. Hence, adder is the basic component used in digital signal processor. DSP architecture is proposed with the energy-efficient goal. Traditional carry select adder contains ripple carry adder block is replaced by parallel prefix adder. By replacing that block and introducing folded tree, we can reduce power used by DSP processors. This architecture can be used in all power constrained DSP applications. In the existing system, folded tree is used in architecture to reduce the number of processing elements, and they used carry look-ahead adder to perform the internal processing element operations. In the proposed system, carry look-ahead adder is replaced by LFA and PA to harness the energy depleted in an application (e.g., DSP application). Power consumption is reduced by 12–15% as compared with the existing algorithms using Cyclone III (EP3C16F484C6).

Finite Impulse Response (FIR) Filter occupied a significant position in most of Digital Signal Processing (DSP) Applications. The behaviour of FIR filters can be realized in software for DSP applications and executed on Digital Signal Processor architectures. These kinds of digital filters consider digital components, digital input and perform mathematical computations to produce digital output. In modern DSP applications demanding area efficient architecture for DSP algorithms while optimizing throughput. This can be achieved by design of hardware architectures for DSP algorithms and apply design optimization techniques to accelerate the throughput and minimize area. This article attempts to develop hardware architectures for FIR Filter and apply the design optimization techniques present in literature. In this article, High Level Synthesis concepts were adapted to develop hardware architecture for FIR filter and optimization techniques have been applied to optimize design attributes like area, throughput and power. Finally, design attributes are summarized after applying optimization techniques and published significant architectural attributes suitable for real life DSP applications.

Field-Programmable Gate Arrays (FPGAs) provide a flexible and efficient platform for implementing Single Instruction, Multiple Data (SIMD) computations, offering advantages over traditional CPUs and GPUs through customizable architectures. This article explores the design considerations, optimization techniques, and practical applications of SIMD operations on FPGAs. We examine how vector processing units, specialized memory organizations, and interconnect architectures can be tailored to application requirements, while investigating methods for datapath optimization, memory access enhancement, and pipeline efficiency. The discussion extends to real-world FPGA-based SIMD applications in digital signal processing, machine learning acceleration, and image/video processing, highlighting how the reconfigurable nature of FPGAs enables performance and energy efficiency improvements for data-parallel workloads across various domains.

Hardware acceleration using field programmable gate arrays (FPGAs) has become increasingly popular for computationally intensive digital signal processing (DSP) applications. Unfortunately, while FPGAs have a reasonably tractable computer aided design (CAD) flow and performance, they have poor power characteristics when compared to direct application specific integrated circuit (ASIC) fabrication. ASICs exhibit better performance and power than FPGAs, but require complex CAD and large non-recurring engineering (NRE) costs. A reconfigurable device that exhibits ASIC-like power characteristics and FPGA-like costs and tool support is desirable to fill this void. Several coarse-grained fabric architectures proposed during the last decade have been focused on performance and area-efficient architectural techniques. Even though power is becoming one of the critical design concerns for semiconductor industry, this issue has not been adequately addressed in the existing coarse-grained fabric architectures. In this paper, a low-power and high-performance hardware acceleration engine for DSP style applications is described. This reconfigurable fabric model is generic and parameterizable allowing design parameters to be adjusted within the architecture. The impact of varying different design parameters such as functional unit granularity, and multiplexer cardinality are studied for their implications on power and performance. The low-power fabric was designed to operate within the SuperCISC processor architecture designed at the University of Pittsburgh

As Field programmable Gate Array (FPGA) technology has steadily improved, FPGAs are now viable alternatives to other technology implementations for high-speed classes of digital signal processing (DSP) applications. In particular, radar front-end signal processing, an application formerly dominated by custom very large scale integration (VLSI) chips, may now be a prime candidate for migration to FPCA technology. As this paper demonstrates, current FPGA devices have the power and capacity to implement a FIR filter with the performance and specifications of an existing, in-system, front-end signal processing custom VLSI chip. A 512-tap, 18-bit FIR filter was built that could achieve sample rates of 5 MHz (with a clock rate of at least 40 MHz) using Xilinx Virtex FPGA technology, and was demonstrated through simulation. Distributed arithmetic was determined to be the most optimal structure for a FPGA FIR design, although future research may show that fast FIR algorithms or filtering in the frequency domain might give better results.

Finite impulse response (FIR) digital filters are extensively used due to their key role in various digital signal processing (DSP) applications. Several attempts have been made to develop hardware realization of FIR filters characterized by implementation complexity, precision and high speed. Field Programmable Gate Array is a reconfigurable realization of FIR filters. Field-programmable gate arrays (FPGAs) are on the verge of revolutionizing digital signal processing. Many front-end digital signal processing (DSP) algorithms, such as FFTs, FIR or IIR filters, are now most often realized by FPGAs. Modern FPGA families provide DSP arithmetic support with fast-carry chains that are used to implement multiply-accumulates (MACs) at high speed, with low overhead and low costs. In this paper, distributed arithmetic (DA) realization of FIR filter as serial and parallel are discussed in terms of hardware cost and resource utilization.

The Number Theoretic Transform (NTT) plays a central role for supporting high-performance polynomial multiplication on Post-Quantum Cryptography (PQC) and Fully-Homomorphic Encryption (FHE). This paper proposes a novel Montgomery-based butterfly to efficiently implement NTTs on FPGAs. This proposal is supported on prime moduli suitable for FHE, which minimizes the requirements to allow the speedup of the computation of the butterfly. A search algorithm is presented to select these moduli, while flexibility is a target in all parameters making the proposed architectures well-suited for FHE and PQC schemes. We experimentally evaluate the effectiveness of the novel butterfly-core on a Xilinx Virtex-7 device. The results show reductions up to 19%, 41%, 37%, and 67% in the number of lookup tables, slices, flip-flops, and Digital Signal Processors (DSPs), respectively, in comparison to the related state of the art. By integrating the proposed butterflies in a complete NTT accelerator, a speedup of up to 1.42 is achieved, while less than half of the number of DSPs are required, when compared to the other proposals. Moreover, the integration of the proposed accelerators to design FHE-based processors is discussed.

The rapid increase in digital signal processing (DSP) applications has generated a strong demand for electrical engineers with DSP backgrounds; however, the gap between industry needs and university curricula still exists. To answer this challenge, a sequence of innovative DSP courses that emphasize hands-on experiments and practical applications were developed for continuing education in electrical and computer engineering. These courses are taught in the evening for night-school students having at least three years of work experience. These courses enable students to experiment with sophisticated DSP applications to augment the theoretical, conceptual, and analytical materials provided in traditional DSP courses. The inclusion of both software and hardware developments allows students to undertake a wide range of DSP projects for real-world applications. Assessment data concludes that the digital signal processor fundamentals course can increase learning interest and overcome the prerequisite problem of DSP laboratory experiments. This paper also briefly introduces representative examples of some challenging DSP applications.

Look Up Table (LUT) is a basic configurable logic element in Field Programmable Gate Arrays (FPGAs). In a commercial product, Static Random Access Memory (SRAM) has been widely used in each LUT to store configured logic. Recently, emerging Resistive RAM (RRAM) has attracted a lot of attention for its high density and non-volatility. In this work, we explore a novel LUT design with bipolar RRAM devices. To obtain design efficiency, a 3D high-density interleaved memory structure is introduced in the proposed LUT. The corresponding peripheral circuits were developed with TSMC 0.18µm technology node. Compared to the traditional SRAM-based FPGA, the RRAM-based LUT demonstrates advantages such as a eliminating initialization stage, a much higher density with 56% area reduction, a bit-addressable write scheme, dynamic reconfiguration, and better flexibility in supporting various configurations.

The logic block of field programmable gate array (FPGA) basic unit is mainly composed of look-up-table (LUT). The conventional LUT using the static random access memory (SRAM), which leads to FPGA almost reach the limitation in term of the density, speed, and configuration overhead. In this paper, a new scheme of improved memristor-based look-up-table (MLUT) is proposed. The MLUT circuit, which is compatible with the mainstream circuit in FPGA. The MLUT effectively solving the limitations of field FPGA and MLUT is more efficient in data transmission than traditional LUT. In addition, the proposed circuit can achieve any combination logic function in MLUT by specific configuration. As a case study, a three-input LUT circuit based on memristor is designed and the correctness of the results is simulated in PSPICE software. The MLUT can replace traditional SRAM-based LUTs and further improve FPGA performance.