Architectural support for quality of service for CORBA objects

Radio Resource Management (RRM) techniques used in Worldwide Interoperability for Microwave Access (WiMAX) can provide for many of the services and features promised by 4G wireless networks, such as supporting multimedia services with high data rates, and wide coverage area, as well as all-IP with Quality of Service (QoS) support and security. In this paper we propose a new scheduling scheme and admission control policy for WiMAX that efficiently enhances performance and utilizes resources, while being fair, practical and in compliance with the IEEE 802.16 specifications. Our scheduler is dynamic and based on hierarchical and ad-hoc models. Our solution provides QoS support to all traffic classes defined by the standard, and it dynamically changes the bandwidth allocation depending on the traffic characteristics and service demands. Simulation results show that the proposed solution can deliver QoS support and be fair to all classes of service in a WiMAX network.

Presents a paradigm that combines the speed of single address spaces with the traditional protection mechanisms found in multiple address space systems such as UNIX. Multiple address spaces are common today for providing safety and security in operating systems. A process in one address space cannot corrupt or compromise memory locations an another process's address space. However, inter-process communication is slow because it is expensive to context switch between address spaces. Single address space systems provide a solution to the problem of slow context switches. In a single address space system, which is typically implemented in a 64-bit address space, all processes shape a common address space. Hence, the need to move between address spaces during inter-process communication is avoided. It is our position that it is not strictly necessary to use a single address space in order to achieve fast inter-process communication. >

This paper describes a global scheme for the support of quality of service (QoS) in CORBA environment. The support of QoS is done through the interaction between two CORBA objects, the micro QoS manager and the object resource manager. A key feature of this scheme is the ability to provide an accurate QoS support according to the application type while enabling a high level of maintenance and reusability. The paper outlines the architectural principles used and describes our implementation in a video-on-demand application context.

As the number of hosts attached to a network increases beyond what can be connected by a single local area network (LAN), forwarding packets between hosts on different LANs becomes an issue. Two common solutions to the forwarding problem are IP routing and spanning tree bridging . IP routing scales well, but imposes the administrative burden of managing subnets and assigning addresses. Spanning tree bridging, in contrast, requires no administration, but often does not perform well in a large network, because too much traffic must detour toward the root of the spanning tree, wasting link bandwidth.

With reference to a distributed context consisting of computers connected by a local area network, we present the organization of a memory management system giving physical support to a uniform, persistent vision of storage according to a single address space paradigm. Our system implements a two-layer storage hierarchy in which the distributed secondary memory stores the valid data items and the primary memory supports a form of data caching, for fast processor access. The proposed system defines a small, powerful set of operations that allow application programs to exert explicit control over the memory management activities at the levels of physical storage allocation, data migration across the network, and the data movements between the secondary memory and the primary memory. The system, that has been implemented in prototype form, is assessed from a number of viewpoints. We show that the storage requirements of the information for memory management are negligible. Moreover, the number of messages necessary to determine the network location of a given data item is low and independent of both the network size and the past movements of this data item in the distributed storage.Copyright © 2000 John Wiley & Sons, Ltd.

: The objective of the Integrated High Performance Distributed System (IHPDS) project is to design, implement, and demonstrate a distributed programming environment that will integrate and support very high bandwidth networks with heterogeneous computer architectures, including parallel and specialized processors, and that will support multiple programming models. The IHPDS project is developing the Photon distributed programming environment to meet the emerging needs of distributed application programmers. Photon provides an object-oriented programming model. This provides users with a consistent view of all services while insulating the user from the implementation details of those services. This enforcement of modularity and the separation of policy and mechanism make the object model a powerful way to build large-scale, distributed applications. Photon is a distributed computing environment that supports distributed application development across heterogeneous machine architectures and programming languages. It is particularly targeted to support the needs of high performance applications. Photon not only supports applications whose components are located within a single local area network, but also supports applications whose components are widely dispersed geographically.

No abstract available.

In component-based software engineering research, much effort has gone into developing specification techniques for software components. There exist many software component specification techniques, from interface description language (IDL), to design-by-contract based, to formal methods. However, much of the focus of the research literature is aimed at component specification for the development of components, not their use. The current best practices for component specification ignore information that is vital in determining if an available, ready to use component contains precisely the functional and extra-functional properties required and if that component can be used in the target environment. These specification techniques do not sufficiently support selection and reuse of software components. This paper evaluates some of the current component specification techniques with respect to the needs of component selection and reuse. From this evaluation, some recommendations made as to advancing the development of component specifications to include the purposes of component selection and reuse.

Paradigm (parallel distributed global memory), a shared-memory multicomputer architecture that is being developed to show that one can build a large-scale machine using high-performance microprocessors, is discussed. The Paradigm architecture allows a parallel application program to execute any of its tasks on any processor in the machine, with all the tasks in a single address space. The focus is on novel design techniques that support scalability. The key performance issues are identified, and some results to date from this work and experience with the VMP architecture design on which it is based are summarized.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

To tackle the significant challenge of achieving the frequency domain and time domain resource allocation on the Geostationary Earth Orbit (GEO) satellite return link, we develop a two‐tier “Carrier Planning‐Timeslot Allocation” cooperative resource‐management framework to optimize system efficiency and different quality of service (QoS) for diverse user demands simultaneously. The Dynamic Planning Carrier Configuration (DPCC) algorithm continuously reconfigures the frequency carrier set through a multi‐layer aggregation and proportional allocation procedure, in which the share granted to each carrier tier is steered by the weighted traffic demand of every priority class and the prevailing channel fading severity. The Timeslot Allocation under Fixed Carriers Set (TAFCS) algorithm initially utilizes a modulation and coding (MODCOD) update mechanism to exploit favorable channel conditions. Then it conducts scheduling in three successive phases “priority‐driven allocation, idle‐slot aggregation and reuse, and residual‐request slicing”. Extensive Satellite Network Simulator 3 simulations show that TAFCS alone outperforms the first‐fit algorithm and the Reserve Channel with Priority (RCP)‐fit algorithm, boosting timeslot utilization and return channel satellite terminal (RCST) response rates by roughly 8%–11% while meeting QoS targets across high‐/medium‐/low‐priority traffic. When DPCC is introduced, the simulation under seven scenarios with diverse traffic and channel dynamics confirms that the DPCC‐TAFCS framework markedly surpasses single‐layer TAFCS on both system efficiency and QoS support, while demonstrating robust effectiveness under harsh link conditions.

The significant performance-to-cost ratio advantage of clusters, combined with recent advances in middleware (programming environment) and networking technologies, has made them the single most popular and fastest growing platform for high performance computing in recent years. While the message passing interface (MPI) still dominates as a means of parallel programming in clusters, it is nevertheless desirable for programmers to program in a single address space, not only across a cluster but also among multiple, likely heterogeneous, clusters so as to significantly extend the computing power of a single cluster. In this paper we propose a distributed shared object (DSO) model based on a distributed hierarchical consistency model (DHCM) protocol for heterogeneous clusters. DHCM, inspired by but significantly improved over the local consistency, is designed to help maintain coherence and consistency in a DSO programming environment and to adapt to different levels of consistency. The notion of adaptive consistency is proposed and partially implemented to improve the efficiency in consistency control, and scalability is addressed as well through the hierarchical structure of the protocol design. We implemented this model purely in Java for portability and heterogeneity. The performance of DHCM is evaluated by executing the LU application chosen from the SPLASH-2 benchmark suite on a 128-node Linux cluster. The experimental results show that the protocol with a hierarchical structure significantly outperforms the protocol with a single-tier in terms of execution time, indicating higher scalability.

This paper presents Weaves, a language neutral framework for scalable execution of legacy parallel scientific codes. Weaves supports scalable threads of control and multiple namespaces with selective sharing of state within a single address space. We resort to two examples for illustration of different aspects of the framework and to stress the diversity of its application domains. The more expressive collaborating partial differential equation (PDE) solvers are used to exemplify developmental aspects, while freely available Sweep3D is used for performance results. We outline the framework in the context of shared memory systems, where its benefits are apparent. We also contrast Weaves against existing programming paradigms, present use cases, and outline its implementation. Preliminary performance tests show significant scalability over process-based implementations of Sweep3D.

Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to manage coherence, found in compute accelerators. In some systems, both types of models are supported using disjoint address spaces and/or physical memories. In this paper we present Cohesion, a hybrid memory model that enables fine-grained temporal reassignment of data between hardware-managed and software-managed coherence domains, allowing a system to support both. Cohesion can be used to dynamically adapt to the sharing needs of both applications and runtimes. Cohesion requires neither copy operations nor multiple address spaces. Cohesion offers the benefits of reduced message traffic and on-die directory overhead when software-managed coherence can be used and the advantages of hardware coherence for cases in which software-managed coherence is impractical. We demonstrate our protocol using a hierarchical, cached 1024-core processor with a single address space that supports both software-enforced coherence and a directory-based hardware coherence protocol. Relative to an optimistic, hardware-coherent baseline, a realizable Cohesion design achieves competitive performance with a 2× reduction in message traffic, 2.1× reduction in directory utilization, and greater robustness to on-die directory capacity.

This paper explores the intersection of operating systems and database systems, focusing on the potential of specialized kernels for cloud-native database systems. Although the idea of custom, DBMS-optimized OS kernels is old, it is largely unrealized due to the demands of hardware compatibility and the reluctance of users to install specialized operating systems. However, the cloud and the database-as-a-service model make custom OS kernels realistic for the first time. Among specialized OS kernel architectures, unikernels stand out for relying on a single address space, eliminating the need for costly process isolation that is provided by general-purpose operating systems. They offer benefits such as the elimination of system call overhead, direct access to hardware, and reduced complexity. Beyond these immediate advantages, unikernels offer a unique opportunity: the possibility to revisit dated POSIX APIs. By allowing direct interaction with modern hardware primitives, unikernels pave the way for the development of novel abstractions that are not confined to the limitations of older APIs, opening doors to a new era of co-designed, high-performance cloud-native data processing systems and OS kernels.

Serverless computing has gained widespread popularity due to its rapid deployment, elastic scaling, and pay-as-you-go advantages. Large-scale pipeline applications designed for big data processing, video analytics, and machine learning are gradually evolving toward the serverless architecture. However, the inefficiency of large data transmission among functions has limited the further adoption of the serverless paradigm in these applications. With the emergence of capability Instruction Set Architecture (ISA), the multi-tenant security isolation model and data transmission methods in the cloud have ushered in new opportunities. This paper proposes Hummer, an efficient communication and data transmission scheme based on the capability ISA. The capability ISA allows multiple functions to run in separate isolation domains in a single address space. Function instances can efficiently share memory by directly passing hardware capabilities. This paper extends the CHERI capability ISA, introducing the novel shared capability and shared capability store tracking (SCST) mechanism to manage the shared memory access rights, enabling a zero-copy communication mechanism. We compare Hummer with existing communication mechanisms and show that it improves data transmission rate by 6 – 40 ×. Redis implemented with Hummer APIs doubles its throughput.