Single address space implementation in distributed systems

The present study tested the dual-component model of working memory capacity (WMC) by examining estimates of primary memory and secondary memory from an immediate free recall task. Participants completed multiple measures of WMC and general intellectual ability as well as multiple trials of an immediate free recall task. It was demonstrated that there are 2 sources of variance (primary memory and secondary memory) in immediate free recall and that, further, these 2 sources of variance accounted for independent variation in WMC. Together, these results are consistent with a dual-component model of WMC reflecting individual differences in maintenance in primary memory and in retrieval from secondary memory. Theoretical implications for working memory and dual-component models of free recall are discussed. (PsycINFO Database Record (c) 2009 APA, all rights reserved).

Presents a paradigm that combines the speed of single address spaces with the traditional protection mechanisms found in multiple address space systems such as UNIX. Multiple address spaces are common today for providing safety and security in operating systems. A process in one address space cannot corrupt or compromise memory locations an another process's address space. However, inter-process communication is slow because it is expensive to context switch between address spaces. Single address space systems provide a solution to the problem of slow context switches. In a single address space system, which is typically implemented in a 64-bit address space, all processes shape a common address space. Hence, the need to move between address spaces during inter-process communication is avoided. It is our position that it is not strictly necessary to use a single address space in order to achieve fast inter-process communication. >

Fifteen high-frequency words were presented to children (ages 8–12), young adults (ages 20–32), and old adults (ages 60–79) for immediate free recall. Estimations of primary and secondary memory showed that children and old adults had lower primary memory than did young adults and that old adults had lower secondary memory than did children and young adults. Suggestions for dealing with lower primary and secondary memory are made, and future research is suggested.

The California Verbal Learning Test (CVLT; Delis, Kramer, Kaplan, & Ober, 1987) was administered to patients with mild to moderate Alzheimer disease (AD) (Group AD; n = 13) and to a control group of normal older adults (Group NC; n = 13) matched on age and education. Two measures were used to determine whether primary memory (PM) is impaired in early AD. One measure, considered a relatively "pure" measure of PM, is based on the procedure developed by Tulving and Colotla (1970) which considers an item to be recalled from PM if no more than six items intervene between its presentation and recall. The other measure is the more commonly used recall from recency. No significant difference between the AD and NC Groups was found, both on the Tulving and Colotla measure, as well as on the recall from recency measure of PM. A significant difference was obtained on two measures of secondary memory (SM), namely, Tulving and Colotla's measure and recall from the primacy and middle regions of the list of words. In comparison to NC, and AD patients showed little evidence of learning over the five trials, and poor retention even over short delays. In addition, the patients with AD showed deficits in clustering words by taxonomic category at recall. We conclude that impairment in PM cannot be used as a diagnostic marker of AD in the early stages of the disease process.

Primary and secondary memory were tested in depressive patients by means of immediate free recall of lists of words in a double blind intraindividual cross-over comparison between ACTH 4-10 in a single s.c. dose and placebo, in connection with the second and third unilateral electroconvulsive treatment (ECT). The results of the study did not show any memory facilitating effect of ACTH 4-10 in immediate recall from primary and secondary memory, after ECT. The results indicate a negative effect of ECT on delayed recall from secondary memory 120 min after ECT.

Object-oriented models are a popular basis for supporting uniform sharing of data and services in operating systems, distributed programming systems, and database systems. We term systems that use objects for these purposes object sharing systems. Operating systems in common use have nonuniform addressing models, making the uniform object naming required by object sharing systems expensive and difficult to implement. We argue that emerging 64-bit architectures make it practical to support uniform naming at the virtual addressing level, eliminating a key implementation problem for object sharing systems. We describe facilities for object-based sharing of persistent data and services in Opal, an operating system we are developing for paged 64-bit architectures. The distinctive feature of Opal is that object sharing is supported in a runtime library, a,bove a single virtual address space that maps all primary and secondary storage in a local area network. This work was supported in part by the National Science Foundation under Grants No. CCR-8619663 and CCR8907666; by the Washington Technology Center; and by Digital Equipment Corporation through the Systems Research Center, DECwest Engineering, the External Research Program, and the Graduate Engineering Education Program. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notico is Siven that copving is bv permission of the Association for Computing Machinery. To copy otherwise. or to republish, requires B fee and/or specific permission. o 1992 ACM 0-89791.539.9/92/0010/0397...$1.50

Objective: To examine cognitive function in very old depressed individuals. Method: Individuals with major depression (MDS) or dysthymia according to the DSM-III-R were compared to mentally healthy regarding tests of verbal ability, inductive logical reasoning, spatial ability, perceptual speed, basic arithmetics, primary memory and secondary memory in a population-based sample of 85-year-olds. Results: Individuals with MDS performed worse than mentally healthy individuals in tests of verbal ability, inductive logical reasoning, spatial ability, perceptual speed and secondary memory. There were no differences between the groups regarding basic arithmetics and primary memory. The poor test performance was mainly associated with psychomotor retardation and decreased concentration in depressed individuals. Memory complaints were not correlated to poor test performance, neither in the mentally healthy nor in the depressed. Conclusion: MDS in elderly individuals is associated with reduced cognitive test performance, especially regarding more complex and time-demanding tests and in tests of secondary memory.

Contemporary discrete GPUs support rich memory management features such as virtual memory and demand paging. These features simplify GPU programming by providing a virtual address space abstraction similar to CPUs and eliminating manual memory management, but they introduce high performance overheads during (1) address translation and (2) page faults. A GPU relies on high degrees of thread-level parallelism (TLP) to hide memory latency. Address translation can undermine TLP, as a single miss in the translation lookaside buffer (TLB) invokes an expensive serialized page table walk that often stalls multiple threads. Demand paging can also undermine TLP, as multiple threads often stall while they wait for an expensive data transfer over the system I/O (e.g., PCIe) bus when the GPU demands a page. In modern GPUs, we face a trade-o on how the page size used for memory management affects address translation and demand paging. The address translation overhead is lower when we employ a larger page size (e.g., 2MB large pages, compared with conventional 4KB base pages), which increases TLB coverage and thus reduces TLB misses. Conversely, the demand paging overhead is lower when we employ a smaller page size, which decreases the system I/O bus transfer latency. Support for multiple page sizes can help relax the page size trade-o so that address translation and demand paging optimizations work together synergistically. However, existing page coalescing (i.e., merging base pages into a large page) and splintering (i.e., splitting a large page into base pages) policies require costly base page migrations that undermine the benefits multiple page sizes provide. In this paper, we observe that GPGPU applications present an opportunity to support multiple page sizes without costly data migration, as the applications perform most of their memory allocation en masse (i.e., they allocate a large number of base pages at once). We show that this en masse allocation allows us to create intelligent memory allocation policies which ensure that base pages that are contiguous in virtual memory are allocated to contiguous physical memory pages. As a result, coalescing and splintering operations no longer need to migrate base pages. We introduce Mosaic, a GPU memory manager that provides application-transparent support for multiple page sizes. Mosaic uses base pages to transfer data over the system I/O bus, and allocates physical memory in a way that (1) preserves base page contiguity and (2) ensures that a large page frame contains pages from only a single memory protection domain. We take advantage of this allocation strategy to design a novel in-place page size selection mechanism that avoids data migration. This mechanism allows the TLB to use large pages, reducing address translation overhead. During data transfer, this mechanism enables the GPU to transfer only the base pages that are needed by the application over the system I/O bus, keeping demand paging overhead low. Our evaluations show that Mosaic reduces address translation overheads while efficiently achieving the benefits of demand paging, compared to a contemporary GPU that uses only a 4KB page size. Relative to a state-of-the-art GPU memory manager, Mosaic improves the performance of homogeneous and heterogeneous multi-application workloads by 55.5% and 29.7% on average, respectively, coming within 6.8% and 15.4% of the performance of an ideal TLB where all TLB requests are hits. CCS CONCEPTS • Computer systems organization → Parallel architectures;

UV2 is SGI's second generation data fusion system. UV2 was designed to meet the latest challenges facing users in computation and data analysis. Its unique ability to perform both functions on a single platform enables efficient, easy to manage workflows. This platform has a hybrid infrastructure, leveraging the latest Intel® EP processors providing industry leading computational power. Due to its high bandwidth, extremely low latency NUMALink®6 (NL6) interconnect, plus vectorized synchronization and data movement, UV2 provides industry leading data intensive capability. It supports a single operating system (OS) image up to 64TB and 4K threads. Multiple OS images can be deployed on a single NL6 fabric, which has a single flat address space up to 8PB and 256K threads. These capabilities allow for extreme performance on a broad range of programming models and languages including OpenMP[1], MPI, UPC[2], CAF[3] and SHMEM. The architecture, implementation and performance of UV2 are detailed.

The fate of primary memory items in free recall

No abstract available.

CORBA is a commercial standard for distributed object computing which shows great promise in the development of distributed programs. Its interface description language (IDL) enables objects to be developed independently of the underlying programming language, operating system, or computer architecture on which they will execute. While this is sufficient in many environments, programs deployed in a wide-area distributed system encounter conditions which are much more hostile and varying than those operating in a single address space or within a single local area network. In this paper we discuss four major problems we have observed in our developing and deploying wide-area distributed object applications and middleware. First, most programs are developed ignoring the variable wide area conditions. Second, when application programmers do try to handle these conditions, they have great difficulty because these harsh conditions are different from those of the local objects they are used to dealing with. Third, IDL hides information about the tradeoffs any implementation of an object must make. Fourth, there is presently no way to systematically reuse current technology components which deal with these conditions, so code sharing becomes impractical. In this paper we also describe our architecture, Quality of Service for CORBA Objects (QuO), which we have developed to overcome these limitations and integrate their solution by providing QoS abstractions to CORBA objects. First, it makes these conditions first class entities and integrates knowledge of them over time, space, and source. Second, it reduces their variance by masking. Third, it exposes key design decisions of an object's implementation and how it will be used. Fourth, it supports reuse of various architectural components and automatically generates others. © 1997 John Wiley & Sons, Inc.

Recent research in working memory has highlighted the similarities involved in retrieval from complex span tasks and episodic memory tasks, suggesting that these tasks are influenced by similar memory processes. In the present article, the authors manipulated the level of processing engaged when studying to-be-remembered words during a reading span task (Experiment 1) and an operation span task (Experiment 2) in order to assess the role of retrieval from secondary memory during complex span tasks. Immediate recall from both span tasks was greater for items studied under deep processing instructions compared with items studied under shallow processing instructions regardless of trial length. Recall was better for deep than for shallow levels of processing on delayed recall tests as well. These data are consistent with the primary-secondary memory framework, which suggests that to-be-remembered items are displaced from primary memory (i.e., the focus of attention) during the processing phases of complex span tasks and therefore must be retrieved from secondary memory.

Data migration schemes are critical to balance the load in storage clusters for performance improvement. However, as NAND flash based SSDs are widely deployed in storage systems, extending the lifespan of SSD storage clusters becomes a new challenge for data migration. Prior approaches designed for HDD storage clusters, however, are inefficient due to excessive write amplification during data migration, which significantly decrease the lifespan of SSD storage clusters. To overcome this problem, we propose EDM, an endurance aware data migration scheme with careful data placement and movement to minimize the data migrated, so as to limit the worn-out of SSDs while improving the performance. Based on the observation that performance degradation is dominated by the wear speed of an SSD, which is affected by both the storage utilization and the write intensity, two complementary data migration policies are designed to explore the trade-offs among throughput, response time during migration, and lifetime of SSD storage clusters. Moreover, we design an SSD wear model and quantitatively calculate the amount of data migrated as well as the sources and destinations of the migration, so as to reduce the write amplification caused by migration. Results on a real storage cluster using real-world traces show that EDM performs favorably versus existing HDD based migration techniques, reducing cluster-wide aggregate erase count by up to 40%. In the meantime, it improves the performance by 25% on average compared to the baseline system which achieves almost the same effectiveness of performance improvement as previous migration techniques.

The significant performance-to-cost ratio advantage of clusters, combined with recent advances in middleware (programming environment) and networking technologies, has made them the single most popular and fastest growing platform for high performance computing in recent years. While the message passing interface (MPI) still dominates as a means of parallel programming in clusters, it is nevertheless desirable for programmers to program in a single address space, not only across a cluster but also among multiple, likely heterogeneous, clusters so as to significantly extend the computing power of a single cluster. In this paper we propose a distributed shared object (DSO) model based on a distributed hierarchical consistency model (DHCM) protocol for heterogeneous clusters. DHCM, inspired by but significantly improved over the local consistency, is designed to help maintain coherence and consistency in a DSO programming environment and to adapt to different levels of consistency. The notion of adaptive consistency is proposed and partially implemented to improve the efficiency in consistency control, and scalability is addressed as well through the hierarchical structure of the protocol design. We implemented this model purely in Java for portability and heterogeneity. The performance of DHCM is evaluated by executing the LU application chosen from the SPLASH-2 benchmark suite on a 128-node Linux cluster. The experimental results show that the protocol with a hierarchical structure significantly outperforms the protocol with a single-tier in terms of execution time, indicating higher scalability.