Architecture and applications of a second-generation digital signal processor

Energy consumption in Digital Signal Processing (DSP) application is a vital parameter of consideration. Mostly DSP applications deplete power. Battery constraint is important in many mobiles, processors, and sensor-related devices. The major critical operations in DSP architecture are multiplication and addition. Multiplication process is performed using repetitive addition. Hence, adder is the basic component used in digital signal processor. DSP architecture is proposed with the energy-efficient goal. Traditional carry select adder contains ripple carry adder block is replaced by parallel prefix adder. By replacing that block and introducing folded tree, we can reduce power used by DSP processors. This architecture can be used in all power constrained DSP applications. In the existing system, folded tree is used in architecture to reduce the number of processing elements, and they used carry look-ahead adder to perform the internal processing element operations. In the proposed system, carry look-ahead adder is replaced by LFA and PA to harness the energy depleted in an application (e.g., DSP application). Power consumption is reduced by 12–15% as compared with the existing algorithms using Cyclone III (EP3C16F484C6).

A lot of modern ultrasonic measurement (UM) applications use digital signal processing (DSP). In many cases DSP comprises a significant part of system hardware and cost, also it sets certain restrictions on measurement speed and signal-to-noise ratio. This paper deals with the influence of the DSP into signal-to-noise ratio and its relevant characteristicsIt presents a concept of DSP exploration in applications. According to this concept the integrated model UM application - DSP architecture is used to select the rational DSP following the application requirements. The exploration is illustrated with the correlational time delay estimation task. The exploration method was suggested and applied in two scientific projects that have done by Ultrasound Research Center and DSP Laboratory at Kaunas University of Technology. During these projects the ultrasonic vision system for mobile robot (project INCO-COPERNICUS No. ERB IC15-CT96-0726) and high precision ultrasonic gas flowmeter have been designed. In both cases signal processing was necessary and the DSP design presented quite serious problem. The model is implemented in software and provides high flexibility. It can be modified for different DSP methods and signals, therefore, it is applicable for the design of various systems.

This paper describes the architecture and applications of a monolithic programmable CMOS VLSI Digital Signal Processor. The processor is based upon the architecture of its predecessor, TMS32020. The processor, which has 544 × 16 bit RAM and 4K × 16 ROM, executes instructions at a rate of 10 Million instructions per second.

Current mobile phone applications demand high performance from the DSP, and future generations are likely to require even greater throughput. However, it is important to balance these processing demands against the requirement of low power consumption for extended battery lifetime. A novel low‐power digital signal processor (DSP) architecture CADRE (Configurable Asynchronous DSP for Reduced Energy) addresses these requirements through a multi‐level power reduction strategy. A parallel architecture and configurable compressed instruction set meets the throughput requirements without excessive program memory bandwidth, while a large register file reduces the cost of data accesses. Sign‐magnitude representation is used for data, to reduce switching activity within the datapath. Asynchronous design gives fine‐grained activity control without the complexities of clock gating, and gives low electromagnetic interference. Finally, the operational model of the target application allows for a reduced interrupt structure, simplifying processor design by avoiding the need for exact exceptions.

A CMOS gate array architecture for digital signal processing (DSP) is presented. The new structure takes into account the high degree of regularity of DSP datapaths and particularly supports the implementation of systolic arrays in connection with a pipelining scheme of one addition per half clock cycle. This reduces both the area and the power consumption by about 21% and 33%, respectively, compared to conventional gate arrays.

Finite Impulse Response (FIR) Filter occupied a significant position in most of Digital Signal Processing (DSP) Applications. The behaviour of FIR filters can be realized in software for DSP applications and executed on Digital Signal Processor architectures. These kinds of digital filters consider digital components, digital input and perform mathematical computations to produce digital output. In modern DSP applications demanding area efficient architecture for DSP algorithms while optimizing throughput. This can be achieved by design of hardware architectures for DSP algorithms and apply design optimization techniques to accelerate the throughput and minimize area. This article attempts to develop hardware architectures for FIR Filter and apply the design optimization techniques present in literature. In this article, High Level Synthesis concepts were adapted to develop hardware architecture for FIR filter and optimization techniques have been applied to optimize design attributes like area, throughput and power. Finally, design attributes are summarized after applying optimization techniques and published significant architectural attributes suitable for real life DSP applications.

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMS, and the chip size is 10 mm x 10.1 mm which is fabricated using a 0.8 μm 2 metal CMOS technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32k (2k x 16 bit) RAM, and 240k (10kx24 bit) ROM. The die size is 8.7 mmx8.3 mm and the chip is fabricated using 0.8 μm CMOS technology.

Exascale computing requires accelerators with ultrahigh power efficiency. Digital signal processors (DSPs), the most important embedded processors widely known for high power efficiency, are rarely explored in the HPC community. We propose a 64-bit general purpose DSP architecture, FT-Matrix2000, which not only integrates the main features of DSPs but also presents several novel enhancements for scientific computing. The FT-Matrix2000 architecture comprises multiple FT-Matrix2 cores and optional RISC CPU cores. The FT-Matrix2 core utilizes a VLIW+SIMD architecture, provides support for double precision operations, and optimizes both the data and control path for scientific computing. Our evaluations show that the performance and efficiency of FT-Matrix2000 are 1107GFLOPS and 92.25%. Compared with the MIC and a 40nm process GPU, FT-Matrix2000 improves the GEMM power efficiency with a factor of 1.49 and 2.68, respectively. We build up a prototype supercomputer with FT-Matrix2000/12. Its HPL efficiency achieves 62.2%, and the performance power ratio is 5.33 GFLOPS/W, which can rank the fourth in the latest Green500 list. These results validate that the FT-Matrix2000 architecture is suitable for scientific computing while maintaining the efficiency of signal processing well. Moreover, the enhancement of FT-Matrix2000 in vector and matrix related computations also enable it to efficiently support deep learning related applications. We have implemented some typical DCNN models on FT-Matrx2000, NVIDIA GPUs, and Vision P6 DSP. The experiments demonstrate that the average computation efficiency of the proposed architecture based on Matrix2000 is about 20 ~ 35% and 8% higher respectively than GPUs and Cadence Vision P6 DSP.

The authors present a VLSI multiprocessor architecture for 2-D digital signal processing. This multiprocessor architecture uses a specially designed high-performance DSP (digital signal processor) as a node in a real-time system. The DSP architecture is based on a computational primitive developed by algorithm decomposition techniques and is used for the real-time implementation of 2-D DLSI (discrete linear shift-invariant) systems. As an example, the authors designed a prototype single-chip DSP chip using 1.25- mu m double-metal CMOS technology to operate with a 40-MHz system clock. This multiprocessor system has a simple interconnection network and a simple control scheme. Each processor in this multiprocessor system operates asynchronously, thus providing very efficient operation. This VLSI architecture also has the advantage that the complexity and number of computations per input do not increase as the size of the input data is increased. Thus, very large 2-D data can be processed in near real time. >

The increasing use of digital signal processors (DSPs) in wireless communications and signal processing necessitates the optimization of compilers to support special hardware features. In this paper, we propose a compiler transformation method for zero overhead loop (ZOL). It supports very long instruction word (VLIW), internal branches and the loops whose iterative times are known at runtime and before execution. In addition, for fully exploiting the special architecture features common in DSPs, the compilation of ZOL transformation is optimized, which further reduces the execution time of loop-intensive applications. The method is implemented on Swift which is a DSP architecture with ZOL and VLIW. Experimental results on benchmark programs show that the proposed method is effective in improving performance.

Research in the field of VLSI digital signal processing (DSP) involves study of algorithms and architectures for VLSI implementation of signal and image processing algorithms, theory of architectures and design methodologies, and computer aided design of VLSI DSP systems which can meet the area-speed-power demands of applications using available technologies. The objective in design and implementation of VLSI DSP systems is to reduce the area and power while meeting the speed requirements of the real-time applications. Although about one and a half decades old, this field is still in its youth. The challenges in meeting the speed-power demands of new applications leads to innovations in theory of architectures. At the same time use of old techniques in new applications allows us to further generalize and extend known principles. Because of these continuing advances and because of lack of text books in this field, it remains difficult to educate practicing engineers and graduate students in this field. This paper presents can overview of two ten-week quarter courses offered at the University of Minnesota to train graduate students in this field. >

Cyclic redundancy check (CRC) is widely used for error detection. For optimal performances, a method has been developed for bit-parallel processing, but it may not take advantage of parallel processor architecture. Here, a method is proposed for using the full power of a very long instruction word (VLIW) digital signal processor (DSP) architecture in CRC computation. The method is at least four times faster for 8, 16 and 32 bits CRC.

In this paper, we compare abilities of two kinds of digital signal processor ( DSP ), M88764 and DSSP1. At first, we implement FIR digital filter and IIR digital filter in using each processor. Next, we implement a discrete Fourier transform by prime factor algorithm in each processor. The numbers of machine cycles and program steps to implement the algorithm in these processing are compared. Moreover, we make it clear how architecture of DSP is suitable for each digital signal processing.

Low dose X-ray image sequences, as obtained in fluoroscopy, exhibit high levels of noise that must be suppressed in real-time, while preserving diagnostic structures. Multi-step adaptive filtering approaches, often involving spatio-temporal filters, are typically used to achieve this goal. In this work typical fluoroscopic image sequences, corrupted with Poisson noise, were processed using various filtering schemes. The noise suppression of the schemes was evaluated using objective image quality measures. Two adaptive spatio-temporal schemes, the first one using object detection and the second one using unsharp masking, were chosen as representative approaches for different fluoroscopy procedures and mapped on to Texas Instrument's (TI) high performance digital signal processors (DSP). The paper explains the fixed point design of these algorithms and evaluates its impact on overall system performance. The fixed point versions of these algorithms are mapped onto the C64x+ TM core using instruction-level parallelism to effectively use its VLIW architecture. The overall data flow was carefully planned to reduce cache and data movement overhead, while working with large medical data sets. Apart from mapping these algorithms on to TI's single core DSP architecture, this work also distributes the operations to leverage multi-core DSP architectures. The data arrangement and flow were optimized to minimize inter-processor messaging and data movement overhead.

Power dissipation is becoming a limiting factor in the realisation of VLSI systems. The principal reasons for this are maximum operating temperature and, for portable applications, battery life. Because of the relatively greater complexity, the power dissipation in Digital Signal Processing (DSP) applications is of special significance, and low-power design techniques are now emerging. This paper provides an overview of these techniques and aims to serve as a bibliography of the key papers relevant to low-power DSP design. In addition, the paper presents indications for potential design directions bearing in mind the architectural complexity and the speed requirements of today's systems. CMOS logic is assumed since this is currently the most commonly used VLSI technology due to its high degree of integration which is in turn allowed by its scaling properties and low power dissipation.