Area-Efficient Design of Modular Exponentiation Using Montgomery Multiplier for RSA Cryptosystem

Modular exponentiation of large number is widely applied in public-key cryptosystem, also the bottleneck in the computation of public-key algorithm. Modular multiplication is the key calculation in modular exponentiation. An improved Montgomery algorithm is utilized to achieve modular multiplication and converted into systolic array to increase the running frequency. A high efficiency fast modular exponentiation structure is developed to bring the best out of the modular multiplication module and enhance the ability of defending timing attacks and power attacks. For 1024-bit key operands, the design can be run at 170MHz and finish a modular exponentiation in 4,402,374 clock cycles.

Improving the computational efficiency of modular operations for embedded systems

RSA is a public key cryptosystem in which encryption and decryption are modular exponentiation functions. Modular exponentiation is achieved by repeated modular multiplications. Montgomery modular multiplication is an efficient algorithm, hence is widely used for RSA public key cryptosystem. Performance of RSA depends on throughput of Montgomery modular multiplication. This paper presents RSA with Early Word based Montgomery modular multiplication. Early word based approach is scalable and Radix 4 Early Word Based Common Multiplicand Montgomery is proposed. RSA cryptosystem is implemented on virtex 5 FPGAs. The processing elements in Early Word based Montgomery use target device resources DSP48E for addition of operands. Two factors: algorithmic approach and use of target device resources have improved the performance of RSA on FPGAs.

Secure transmission of data in a system over the network makes use of various cryptographic techniques. A good and efficient cryptosystem would play a crucial role in providing security services as Data-integrity, Confidentiality, and Authenticity. The security aspect of a cryptosystem is dependent on the computational difficulty involved in solving the mathematical problems involved in the cryptographic technique. Modular exponentiation which makes use of repeated modular multiplication is a tedious process, which is the core operation utilized in cryptosystems. So one can say that the performance of a cryptosystem confides in the performance of modular multiplication and exponentiation. Montgomery multiplication is considered to be a method for performing fast modular multiplication. In this paper comparative study of Montgomery multiplier for various bits is carried out by implementing in Spartan 3E FPGA board and it's different parameters are categorically analyzed.

For modern cryptographic systems, the public key cryptosystem such as RSA requires modular exponentiation (M E mod N). The M, E and N are either as large as the 1024-bit integers or even larger, it is not a very good idea to directly compute M E mod N. Recently, there are many techniques have been invented to solve the time-consuming computations of such time-consuming modular exponentiation. Among these useful algorithms, the “binary (square-and-multiply) algorithm” reduces the amount of modulo multiplications. As the “signed-digit representation algorithm” has the property of the nonzero digit occurrence probability equals to 1/3, taking this advantage, this method can more effectively decrease the amount of modular multiplications. Moreover, by using the technique of recording the common parts in the folded substrings, the “folding-exponent algorithm” can improve the efficiency of the binary algorithm, thus can further decrease the computational complexity of modular exponentiation. In this paper, a new modular exponentiation algorithm is proposed which based on the binary algorithm, signed-digit representation, and the folding-exponent technique. By using the parallel processing technique, in our proposed method, the modular multiplications and modular squaring can be executed in parallel, and thus lower down the computational complexity to k + 3 multiplications. As modular squaring operation over GF(2 n ) is carried out by a simple cyclic right shift operation, the computational complexity of our proposed method can be further reduced to 29k/36 + 3 multiplications.

Modular calculations are widely used in many applications, especially in public key cryptography. Such operations are very time consuming, due to their long operands. To improve the performance of these calculations, many methods have been introduced. Montgomery modular multiplication is an example of such a solution to enhance the performance of modular multiplication and modular exponentiation. The radix-2 version of this method is simple and fast for hardware implementation, where multi-operand adders are required for its implementation. So far, Carry-Save-Adder (CSA) gives the best performance for multi-addition. In this paper, we propose a new recoding method for the Montgomery modular multiplier to enhance its performance. This is done through replacing CSA blocks with new blocks that have better performances than CSA in multi-addition calculations. With this replacement, we can theoretically have up to 40% reduction in area gates. In our experiments, we obtained 5.8% area reduction and 3% speed improvement in a hardware implementation. The idea behind our proposed method is the use of bitwise subtraction operator, where no carry propagation is needed. This recoding method of operands can also be used in many aspects of computer arithmetic, algorithms and computational hardware, such as multiplication, exponentiation and etc., in order to enhance their performances.

A new algorithm, Square-and-Multiply for Modular Exponentiation (SMME), is proposed to calculate a modular exponentiation that is the core arithmetic function in RSA cryptography. The SMME scans the exponent form its MSB and pre-computes a set of exponents to the maximum bit length of l. These pre-computed exponents are stored in a look-up table. By using the look-up table, the number of multiplications required for modular exponentiation can be reduced. Modular multiplications are performed using a modified Montgomery's algorithm. The SMME takes in the order of n<SUP>2</SUP>(1 + 1(2l)) cycles to execute one n-bit modular exponentiation. The memory size to accommodate the pre- computed exponents is a 2<SUP>l-1</SUP> (n + 1)-bit RAM. The SMME, with its regularity and local connections in a systolic array, makes it suitable for VLSI implementation. A 64-bit modular exponentiation chip is being designed using a 0.8 micrometers CMOS standard cell library from AMS. The simulation result show that at 25 MHz, the throughput is approximately 236 KBps; and an estimation of 40 KBps for a 512-bit exponent.

Efficient computation of the modular exponentiations is very important and useful for public-key cryptosystems. In this paper, an efficient parallel binary exponentiation algorithm is proposed which based on the Montgomery multiplication algorithm, the signed-digit-folding (SDF) and common-multiplicand-multiplicand (CMM) techniques. By using the CMM technique of computing the common part from two modular multiplications, the same common part in two modular multiplications can be computed once rather twice, we can thus improve the efficiency of the binary exponentiation algorithm by decreasing the number of modular multiplications. By dividing the bit pattern of the minimal-signed-digit recoding exponent into three equal length parts and using the technique of recording the common parts in the folded substrings, the proposed SDF-CMM algorithm can improve the efficiency of the binary algorithm, thus can further decrease the computational complexity of modular exponentiation. Furthermore, by using the proposed parallel SDF-CMM Montgomery binary exponentiation algorithm, on average the total number of single-precision multiplications can be reduced by about 61.3% and 74.1% as compared with Chang-Kuo-Lin's CMM modular exponentiation algorithm and Ha-Moon's CMM Montgomery modular exponentiation algorithm, respectively.

Details are given here of how to generalise Brickell's fast modular multiplication algorithm to when the number representations have a general 2-power radix. Correct action depends upon the satisfaction of a complicated inequality and speed upon the use of a redundant number system to enable parallel digit operations. The effect of varying the radix on the efficiency of hardware implementations is considered. Improved efficiency has repercussions in public key cryptography where the RSA encryption scheme may use this type of algorithm for its modular exponentiations. However, it is shown that there is no advantage in taking a very large radix, although a small increase above 2 is beneficial.

Modular multiplication forms the basis of many cryptographic functions such as RSA, Diffie-Hellman key exchange, and ElGamal encryption. For large RSA moduli, combining the fast Fourier transform (FFT) with McLaughlin's Montgomery modular multiplication (MLM) has been validated to offer cost-effective implementation results. However, the conditional selections in McLaughlin's algorithm are considered to be inefficient and vulnerable to timing attacks, since extra long additions or subtractions may take place and the running time of MLM varies. In this work, we restrict the parameters of MLM by a set of new bounds and present a modified MLM algorithm involving no conditional selection. Compared to the original MLM algorithm, we inhibit extra operations caused by the conditional selections and accomplish constant running time for modular multiplications with different inputs. As a result, we improve both area-time efficiency and security against timing attacks. Based on the proposed algorithm, efficient FFT-based modular multiplication and exponentiation are derived. Exponentiation architectures with dual FFT-based multipliers are designed obtaining area-latency efficient solutions. The results show that our work offers a better efficiency compared to the state-of-the-art works from and above 2048-bit operand sizes. For single FFT-based modular multiplication, we have achieved constant running time and obtained area-latency efficiency improvements up to 24.3 percent for 1,024-bit and 35.5 percent for 4,096-bit operands, respectively.

Rivest, Shamir, Adleman (RSA) algorithm can be used in cryptography to send confidential messages in secure manner. RSA cryptosystem is based on modular multiplication to factorize the large integers. Montgomery modular multiplication can be used as modular multiplication because it is one of the efficient and fastest modular multiplication. Montgomery algorithm is based on add and shift operation, so Carry save adder (CSA) can be used in order to overcome the carry propagation at each addition. In this Montgomery multiplier, the CSA choses the operands and converts the addition result from carry save format to binary form. Accordingly, the architecture can use less hardware and give short critical path delay to do one modular multiplication. In this paper, the Montgomery modular multiplication uses a modified or configurable Carry save adder (CCSA). The CCSA is designed with one full adder and two half adders to reduce the delay. Still CCSA suffers from high power consumption. In order to reduce the power consumption, the full adder used in CCSA with two multiplexers has been proposed. The proposed Montgomery modular multiplier has the capability to provide 26% average reduction in power when compared with previous designs.

Modular exponentiation is a cornerstone operation to several public-key cryptosystems. It is performed using successive modular multiplications. Clearly, one needs to reduce the total number of modular multiplication required. In this paper, we propose four hardware implementations for computing modular exponentiations using the m-ary method. During this step, the first implementation pre-computes all powers while the second computes only those that are necessary. The main difference between the first two implementations resides in the pre-processing step. However, the first implementation requires less hardware area than the second. The last two do require any pre-processing of the exponent. One of these two implementations is hardware only and the second uses the co-design methodology. We compare these two implementations using the performance factor, which takes into account both space and time requirements.

Fast hardware for modular exponentiation with efficient exponent pre-processing

In order to make the typical Montgomery's algorithm suitable for various lengths RSA, this paper proposes a scheme for an expandable RSA coprocessor. This design allows for cascading the hardware of Process Elements when larger modulo are required. The proposed design uses optimized Montgomery's modular multiplication Algorithm. The proposed architecture has distinctive features, i.e. not only the computation speed is significantly fast but also the hardware overhead is drastically decreased.

Modular multiplication is an integral part of RSA cryptosystems and its performance heavily determines the performance of the encryption hardware. This paper provides a hardware implementation of Montgomery's modular multiplication algorithm using iterative architecture. The propsed design is implemented in Verilog HDL and simulated functionally using ModelSim Altera 10.1E. The synthesis is performed using Altera Quartus II 9.1 with target FPGA board Altera DE2-70. The proposed design consumes 17540 logic elements with 15480 LUT and takes 2048 clock cycles to perform multiplication process. Based on trade-off parameter AT2 measure, the proposed design offers the best performance among other designs.