Assembly language through the Java virtual machine

This paper traces the history of computer architecture courses in electrical engineering departments. Previously unpublished data from the Fall 1972 COSINE survey are given to show current computer architecture course offerings and texts. Computer architecture courses offered in 1972-73 are analyzed, compared with ACM and COSINE recommendations, and classified into five categories: introductory computer engineering courses with a computer architecture flavor, software-oriented computer organization courses, hardware-oriented computer organization courses, case study courses, and topical seminars. Future trends in computer architecture education are predicted.

The Digital Logic and Computer Architecture related courses are one of the key knowledge areas in Computer Science (CS) used to enhance students' understanding of Boolean algebra, logic gates, registers, arithmetic logic units, etc. and provides insights how software and hardware are related in a computing system. Experimental Centric based Instructional Pedagogy (ECP) with portable laboratory instrumentation might provide real hands-on experience to obtain a practical understanding of the concepts at a lower cost compared to virtual hands-on laboratories. This paper presents the initial adaptation of an evidence-based, experiment-focused teaching approach to introduce the fundamentals of digital logic concepts using the commercial ADALM 1K Active Learning Module in a Computer Architecture course for the first time in the CS department at a university serving predominantly minority students. To evaluate the impact of the ECP on student performance in the Computer Architecture course, we conducted three different evaluations, which are class observation, signature assignment, and the Motivated Strategies for Learning Questionnaires (MLSQ) survey. The results of the Classroom Observation Protocol for Undergraduate STEM (COPUS) show more student engagement when ECP is implemented; the output of the signature assignment shows an increase in students' learning outcomes; and the MLSQ survey, which tests the students' motivation, critical thinking, curiosity, collaboration, and metacognition, ascertains the effect of the ECP on the CS students who participated in the experiment.

Most computer architecture courses are geared toward the classical von Neumann style of computer architectures, mentioning only in passing other models such as data flow computation. This is unfortunate, due to the high degree of parallelism possible using data flow. We present an alternative course, designed as an elective in computer architecture for upper level undergraduate or graduate students, that presents a side-by-side comparison of von Neumann and data flow architectures.Our teaching environment is based on Simple Arithmetic SISAL (SAS), a subset of the applicative programming language SISAL, which we designed for both teaching about and research into data flow architectures. SAS runs in a highly integrated environment, allowing students to implement their program on a von Neumann architecture, then observe its execution through a data flow simulator. The environment runs on a standard IBM-style personal computer, providing a cost-effective platform for presenting the course.

This paper describes our experiences with closed laboratories in a computer architecture course and highlights the development of a capstone project. We advocate the use of software as a cost effective means of supporting analysis, design, and experimentation. Improvements to the course in regards to content, environment for learning, student perception, skills accomplished and retained, and instructor involvement are outlined. Several labs are summarized, including the capstone project tying together all aspects of machine organization. We conclude that integrating design education into computer science with the logic simulator lab approach is worthy of our continued efforts.

Introductory-level computer architecture courses often rely on programs with a graphical user interface (such as Logisim) for processor design projects. While these tools provide an easy introduction into logic design, they can detach students from real-world design constraints such as ISA standard tests, and real-world ramifications such as timing and area. This paper introduces a testing flow based on open-source tools that allows Logisim-based designs to be built into ISA-test-compatible simulation binaries, synthesized into gate netlists, and compared for similarity. This flow was used in UC Berkeley's fall 2020 Great Ideas of Computer Architecture course; out of 695 project submissions, over 96% achieved highly-functional designs as measured by the presented infrastructure. CCS CONCEPTS •Social and professional topics $\rightarrow$ Computer engineering education; •Computer systems organization $\rightarrow$ Reduced instruction set computing; Pipeline computing. ACM Reference Format: Ryan Lund, Connor McMahon, Dan Garcia, and Borivoje Nikolić. 2021. Improved Processor Design Project Testing. In Proceedings of WCAE '21. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/1122445.1122456

For several years, the introductory assembly language course at Indiana-Purdue at Fort Wayne has used “structured” assembly language on an IBM System 370. A later course makes use of VAX-11 MACRO assembly language on a VAX 11/780. This paper shows how the major constructs for structured programming may be implemented in VAX-11 MACRO. The scheme involves assembly language templates for each of the constructs, a standard labeling scheme, and a commenting method which reflects the structure of the program.

There is no doubt that the most difficult topic to teach in a Computer Architecture and Organization course is microprogramming. In this paper the author describes a Pascal programming project in which the students write a simulator for a microprogram. The project has been assigned several times with very satisfying results for both the instructor and the students.

While substantial research has demonstrated that active learning pedagogies are better for learning than passive lectures, we need to understand the trade-offs between different active learning pedagogies. Computer Architecture at Midwestern University has historically been taught using active lectures, introducing content with a few clicker questions. In Fall 2018 (N = 363), short video lectures were made available to students as a supplemental resource. In Spring 2019, the instructor flipped the course, requiring students to watch the video lectures and complete an assignment before attending class. Two versions of the course were taught concurrently, using the same homework assignments, machine problems, and examinations but with different in-class pedagogies. Version SP19PI (N = 179) was taught using peer instruction. Version SP19CP (N = 73) was taught using collaborative problem solving, organizing students into teams of 3 to work on problems. Students completed surveys that measured their perceptions of time spent on the course, course difficulty, perceptions of stress, and sense of belonging. We compare students' performance on midterm exams and their non-cognitive outcomes to examine the relative effects of these different active learning pedagogies. We find that both flipped offerings (peer instruction and collaborative problem solving) benefited students beyond active lectures. Peer instruction (SP19PI) made learning more efficient. Collaborative instruction (SP19CP) provided greater social support for learning and eliminated gender grade disparities.

This Innovative Practice Full Paper presents a framework for generating computer-based exams for complex engineering systems (such as cache memories) that can be machine graded while still offering partial credit for students. Complex multi-faceted engineering systems often require long, multi-part problems to fully assess students’ understanding of those systems. Cache memories represent one such system in computer architecture courses. Traditionally, we assessed students’ understanding of caches using comprehensive, multipart questions in a paper-based exam. Grading these exams was time-consuming and relied on subjective grading. To cope with rising enrollment, we sought to address these issues by developing machine administered and gradable exams that did not heavily rely on multiple-choice questions or exact numerical responses. Additionally, this system needed to provide partial credit, a common expectation of our students. We developed a cache simulator to use as a back-end for our questions. We used the simulator to develop exam questions and new homework assignments to help students practice cache memory concepts. To give students access to fair partial credit, we allowed multiple submissions for the exam questions with limited feedback. We also awarded partial credit for answers within certain tolerance of the correct answer. The partial credit awarded reduced as deviation from the correct answer increased. Consequently, students could correct minor mistakes or propagating errors which are common reasons for awarding partial credit. To evaluate the effect of the switch from paper-based to computerized exam, we ported questions from one of our paper-based exams to a computerized exam. We evaluated the differences in student performance on paper-based version and the computerized version of the questions and found mixed results with students performing comparably or better than the paper-based exam on the computer-based exam. We also surveyed students about their experience with the computer-based exam. Students overwhelmingly indicated a preference for the computer-based exam. We believe that ideas from our work can be used to automate generation, administration, and grading of complex multi-part questions in engineering disciplines beyond computer architecture.

While the Java Virtual Machine (JVM) plays a vital role in ensuring correct executions of Java applications, testing JVMs via generating and running class files on them can be rather challenging. The existing techniques, e.g., ClassFuzz and Classming, attempt to leverage the power of fuzzing and differential testing to cope with JVM intricacies by exposing discrepant execution results among different JVMs, i.e., inter-JVM discrepancies, for testing analytics. However, their adopted fuzzers are insufficiently guided since they include no well-designed seed and mutator scheduling mechanisms, leading to inefficient differential testing. To address such issues, in this paper, we propose SJFuzz, the first JVM fuzzing framework with seed and mutator scheduling mechanisms for automated JVM differential testing. Overall, SJFuzz aims to mutate class files via control flow mutators to facilitate the exposure of inter-JVM discrepancies. To this end, SJFuzz schedules seeds (class files) for mutations based on the discrepancy and diversity guidance. SJFuzz also schedules mutators for diversifying class file generation. To evaluate SJFuzz, we conduct an extensive study on multiple representative real-world JVMs, and the experimental results show that SJFuzz significantly outperforms the state-of-the-art mutation-based and generation-based JVM fuzzers in terms of the inter-JVM discrepancy exposure and the class file diversity. Moreover, SJFuzz successfully reported 46 potential JVM issues, and 20 of them have been confirmed as bugs and 16 have been fixed by the JVM developers.

Many widely used, latency sensitive, data-parallel distributed systems, such as HDFS, Hive, and Spark choose to use the Java Virtual Machine (JVM), despite debate on the overhead of doing so. This paper analyzes the extent and causes of the JVM performance overhead in the above mentioned systems. Surprisingly, we find that the warm-up overhead, i.e., class loading and interpretation of bytecode, is frequently the bottleneck. For example, even an I/O intensive, 1GB read on HDFS spends 33% of its execution time in JVM warm-up, and Spark queries spend an average of 21 seconds in warm-up.The findings on JVM warm-up overhead reveal a contradiction between the principle of parallelization, i.e., speeding up long running jobs by parallelizing them into short tasks, and amortizing JVM warm-up overhead through long tasks. We solve this problem by designing HotTub, a new JVM that amortizes the warm-up overhead over the lifetime of a cluster node instead of over a single job by reusing a pool of already warm JVMs across multiple applications. The speed-up is significant. For example, using HotTub results in up to 1.8X speedups for Spark queries, despite not adhering to the JVM specification in edge cases.

Students learn better when they both hear and do. In computer architecture courses “doing” can be difficult in small schools without hardware laboratories hosted by computer engineering, electrical engineering, or similar departments. Software solutions exist. Our success with George Mills' Multimedia Logic (MML) is the focus of this paper. MML provides a graphical computer architecture solution with convenient I/O support and the ability to build and emulate a variety of computer designs. It has proven highly motivational to upper division computer science students designing and constructing emulated computers. Student projects resulted in excellent student understanding of the detailed inner workings of computers. Students also developed better teamwork skills and produced useful training aids for the lower division computer organization class. Designs implemented include 8 bit and 16 bit von Neumann and Harvard architectures, from single cycle to 12 cycle instructions. Issues resolved during the learning process include timing, initialization, instruction set architecture, and I/O and assembler design. We discuss pedagogical issues involved in using MML to implement instructor and student computer designs. MML is compared to using a hardware-based Intel 8085 microprocessor basic systems course.

This paper describes the undergraduate computer architecture courses and laboratories introduced at Georgia Tech during the past two years. A core sequence of six required courses for computer engineering students has been developed. In this paper, emphasis is placed upon the new core laboratories which utilize commercial CAD tools, FPGAs, hardware emulators, and a VHDL based rapid prototyping approach to simulate, synthesize, and implement prototype computer hardware.

This work resulted from an investigation of the activities component of group dynamics in collaborative (or cooperative) groups for two undergraduate sections of computer architecture taught in spring 2002. A cooperative group is a special type of small group consisting of two to four persons. Collaborative learning as used here is a central component of the author devised integrative cooperative learning teaching technique. The hypothesis for this study is that the greater a student's level of within group course related activities for the imposed course assignments, the higher the student's relative course outcomes. To examine this hypothesis, an analysis of the relationship between a student's group activity and course outcomes was done. The sources of data were the student coordinator assessments and student journals compiled throughout the semester. The results of the analyses of the 63 students in the two sections of the undergraduate computer architecture course substantiated the hypothesis that the more a student participates in out-of-class collaborative academic group activity, the greater the student's achievement.

He significantly contributed to research and development of the image processing, classification, and retrieval methods extensively used in the NLM's Open-i Search Engine for biomedical literature. Dr. Rahman has good expertise in the fields of Computer Vision, Image Processing, Information Retrieval, Machine Learning, and Data Mining and their application to retrieval of biomedical images from large collections. Since joining Morgan, Dr. Rahman also has