Assembly Technology for FO-MCM with HBM in HPC Application

The rapid advancement of artificial intelligence (AI) has propelled the demand for high-performance computing (HPC) systems capable of handling vast amounts of data. This necessitates improvements in data processing speed within system-on-chip (SoC) units and efficient data transmission between SoC and high-bandwidth memory (HBM). Advanced packaging solutions, particularly the silicon interposer and organic interposer, have emerged to address these challenges. This article delves into the thermo-mechanical performance of 2.5-D packages with an organic interposer, focusing on warpage management during fabrication and stress analysis induced by coefficient of thermal expansion (CTE) mismatches. The study employs finite element analysis (FEA) modeling to evaluate the impact of various factors on warpage behavior and stress levels. Parametric studies on material selection and interposer geometric design reveal crucial insights. Specifically, reducing bridge die and redistribution layer (RDL) thickness mitigates warpage at the controlled collapse chip connection (C4) level, albeit with adverse effects on BGA level warpage. Material selection significantly influences warpage behavior. Organic materials with higher CTE reduce the mismatch between the interposer and the substrate but it is adverse for the interconnection between chiplets and interposer. Moreover, stress analysis indicates the organic interposer’s effectiveness in reducing interconnection stress compared to silicon interposers. This research contributes valuable insights into the design and optimization of advanced packages with bridges embedded in organic interposers, providing guidelines for material selection and geometric design to enhance reliability and functionality. The findings facilitate the development of advanced packaging solutions capable of meeting the demands of AI-driven applications in challenging operational environments.

Recently, 2.5D package structure such as using silicon interposer is used for high end sever and HPC (High Performance Computing) with high density connection between logic device and memory device. We are developing high density organic package called i-THOP® (integrated-Thin film High density Organic Package) 2.3D type combining organic interposer and build-up substrate. The organic interposer was mounted on build-up substrate. Interconnection between organic interposer and build-up substrate was consisted of copper post and Sn-Bi solder. The bonding process was applied by using the pre-applied NCF (Non-Conductive Film) method. Interconnection was achieved under 200 degrees C by using Sn-Bi solder. The good wettability of Sn-Bi solder was observed at joint portion with minimum 200 μm pitch and no NCF void was confirmed by SAT (Scanning Acoustic Tomography). After that, die assembly was evaluated. The good wettability of solder joints of assembled small die and large die was confirmed with minimum 40 μm pitch. Sn-Bi solder joints were also stable without re-melting after die assembly and stiffener attach process. The thermal warpages of i-THOP® 2.3D type was measured after organic interposer stacking, die assembly and stiffener attach. The warpage without die was small at approximately 20 μm at 30 degrees C and almost no change from 30 degrees C to 250 degrees C. However, the warpage with die was large at 300 μm at 30 degrees C. After stiffener attach process, the thick stiffener over 2.0 mm could reduce warpage below 200 μm that is the criteria of 1.0 mm pitch BGA (Ball Grid Array). The reliability tests of TC (Temperature Cycling), HTS (High Temperature Storage Life), u-HAST (unbiased-Highly Accelerated Temperature and Humidity Stress Test) and b-HAST (biased-Highly Accelerated Temperature and Humidity Stress Test) were carried out. The criteria of TC 1000cycles, HTS 1000 hours, u-HAST 192 hours and b-HAST 96 hours were passed.

The continuing advancement of semiconductor devices steadily increase the number of global interconnects and higher I/O counts thus driving more the importance of smaller feature size interconnects. One of the most difficult technical challenge for interconnects involves new material development, however, it is believed that mitigation of the impact of size scaling such as its aspect ratio (thickness/width) and spacing could fill the gap for high dense packaging requirement brought by Moore's Law. The next generation substrate design rules require a process capability with less than 50um pitch to accommodate leading-edge mobile applications such as Wide I/O memory-Logic packaging integration. In this paper, we describe an organic interposer that is capable of providing high density interface between chips with large I/O counts therefore could be an attractive low-cost 2.1D packaging solution. Our concept can demonstrate ultra fine line interconnects with width/space below 5um with microvias having pitch below 50um which can be effective solution for high density routing. This feature enables the ICs to be attached directly to the substrate therefore eliminating the need for a silicon interposer needed in conventional 2.5D package architecture. Microvia formation using photo-imageable material is another key feature of our organic interposer offering favorable cost efficiency for designs requiring very large numbers of microvias. The buildup layers could be vertically connected by microvias with min. 10um diameter using this process. Aside from the simplicity in supply chain, the high density organic interposer has the potential to meet both power and bandwidth requirement therefore can be considered an incremental move from conventional system-in-package providing flexibility in performance and yield capacity that allows integration of advanced logic and memory devices. We will present our various feasibility results of electrical/mechanical performance obtained from our fabricated test vehicles.

Stacking of many functional chips in a 3D stack package leads to high heat dissipation. Therefore a new platform technology is required to assemble chips vertically and remove the heat effectively. A 3D stacked package with silicon interposers is developed to integrate one ASIC and two memory chips in a package. Electrical connections in the silicon interposer are formed by through silicon via. Silicon has much high thermal conductivity than organic interposers, which reduces drastically the package thermal resistance. Thermal performances of the 3D package are analyzed and thermal enhancement methods like thermal vias, thermal bridging are evaluated. The designed package is having 5 times lesser thermal resistance compared to the package with organic substrate. An additional silicon heat spreader is attached to the package for high power application. Numerical analysis and experimental validation are carried out. The designed 3D stack package is found suitable for 20 watts heat dissipation

In this study, the recent advances and trends in multiple system and heterogeneous integration with through-silicon via (TSV)-less interposer (organic interposer or 2.3-D IC integration) will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of multiple system and heterogeneous integration with TSV-less interposer. Also, some recommendations of 2.3-D IC integration will be provided.

The most singular focus of the electronics industry during the last 50 years has been to miniaturize ICs by miniaturization of transistors and on-chip interconnections. Two major problems are foreseen with this approach; (1) electrical leakage and (2) the lack of improved electrical performance beyond 16nm. As a result, the industry is transitioning from the current SOC-based approach to a through-silicon-via (TSV) based 3D IC-stacked approach. However, a major challenge remains; these 3D ICs need to be interconnected to other ICs with a much higher number of I/Os than are available with current ceramic or organic interposers. While silicon interposers currently in development can provide these high I/Os, they cannot do so at low enough cost. In this extended abstract, 3D Glass Solutions, a division of Life BioScience, Inc., presents our efforts in glass interposer microfabrication. Glass interposers possess many advantages over silicon interposers including: cost, production time, and scale. 3D Glass Solution’s APEX™ Glass ceramic is a photo-sensitive material used to create high density arrays of through glass vias (TGVs) using three simple processing steps: exposure, baking, and etching. To date, we have been successful in producing large arrays of 12 micron diameter TGVs, with 14 micron center-to-center pitch, in 125 micron thick APEX™ Glass ceramic. This extended abstract covers (1) on our efforts producing high aspect ratio TGVs in ultra thin (75–250 micron) APEX™ Glass ceramic wafers, (2) maximum TGV aspect ratios, and (3) TGV fidelity and limits of manufacturing.

Heterogeneous integration for system in package (SiP), flip-chip integration in 3D packaging and embedded ICs in advanced Printed Circuit Boards (PCB) are all pushing the limits for low profile packaging. Advanced polymer materials applied in Semiconductor-on-Polymer™ wafer level chip scale packaging (SoP WLCSP) are gaining traction as a high reliability ultra-thin packaging solution. The 2019 roadmap for Heterogeneous Integration defines heterogeneous Integration (HI) as the integration of separately manufactured components into a higher-level assembly that provides enhanced functionality and improved operating characteristics. The development of this technology is a significant industry challenge that can evolve quickly with the application of SoP polymer based packaging. At advanced nodes, die yield falls exponentially with die size. Splitting a large monolithic SoC into smaller tightly coupled die, is an attractive alternative considering that die cost per unit area is escalating. The smartphone industry has been an early adopter of HI technologies in the use of SiP for multiple generations, essentially for the advantages in miniaturization, modularity for co-design, and enhanced generation-over-generation performance. The application processor is almost always on the most advanced node and housed in a Package on Package (PoP) configuration with memory component(s) stacked on top of this ASIC. Teardowns of the Package-on-Package (PoP) packages for Apple XSMax, Samsung Galaxy S9+, and Huawei 20 Pro have shown the utilization and need for continued z-axis thickness scaling. Implementation of SoP CSP for package in package integration or for chip on thin PCB, interposer or flex can provide another package capability for evolution of multi-layer heterogeneous integration. Reliable ultra-thin polymerized die have the potential to tackle the third dimension (z-axis) of total IC package volume in 3D integration. SoP die can replace current full thickness or partially thinned (typically >250µm) die with <35µm package thickness devices. In addition, the SoP process has the potential to extend package roadmaps enabling smaller higher performance packages in several areas, including Fan-Out (FO). Thin bridge die could simplify localized high IO for substrates. Thin embedded IPD (integrated passive devices) have the potential to increase the capability and shrink the size of substrate process based passives, similar to the performance increase for wafer based devices versus printed electronics. In addition thin high IO die could allow simplified embedding in substrates. The differentiation of PCBs, interposers and flex circuits is starting to blur. Package integration within the layers of these devices can create embedded ICs that take less system space and improve system performance. Traditionally, manufacturing steps to place an IC within the board substrate vary and require space to be created for the component body, in the form of a cavity for traditional packaged ICs. In Integrated module board (IMB), components are aligned and placed inside a cavity that is routed to the core laminate by controlled-depth routing. The cavity is filled with molding polymer to ensure chemical, mechanical, and electrical compatibility with the substrate. Isotropic solder is impregnated with the polymer to form reliable solder joints when the embedded part is laminated into the stack. Polymerized ICs in SoP CSP eliminate cavity requirements and molding polymers for IMB. Chip in polymer (CIP) approaches use thin chips in built up dielectric layers of PCBs, rather than integrating them into the core layers. When SoP CSP is applied, it is feasible to achieve the same capability, but with a much smaller z-axis and without creating a surface geography perturbation. This presentation will include an introduction to SoP CSP utilizing advanced polymer technology for accelerating evolution of HI, PoP and Embedded applications.

The semiconductor industry is continuously evolving to meet the demands of an increasingly connected and data-driven world. As traditional Moore's Law scaling becomes more challenging, the next frontier in advanced packaging is heterogeneous integration (HI), with an emphasis on key technologies such as silicon interposers, hybrid bonding, and fan-out wafer-level packaging (FOWLP). HI involves combining various components and technologies, including diverse materials, devices, and functions, within a single package to enhance system performance, functionality, and miniaturization. This paper explores the emerging paradigm of heterogeneous integration with a focus on these key enabling technologies. I will discuss the principles and capabilities of silicon interposers, which provide a versatile platform for integrating different semiconductor components, reducing interconnect length, and enhancing signal speed and power efficiency. Hybrid bonding, a revolutionary technique for precise, low-temperature chip-to-chip connections, is another critical aspect, enabling a new level of flexibility in the assembly of complex systems. Furthermore, I will examine the advantages and versatility of Fan-Out Wafer-Level Packaging (FOWLP), which enables the integration of multiple semiconductor devices and heterogeneous components on a single wafer. This approach not only reduces form factors but also offers cost-effective and high-performance solutions for a wide range of applications. This paper discusses how the synergy of silicon interposers, hybrid bonding, and FOWLP has brought about the benefits of HI, such as improved system performance, cost-effectiveness, and time-to-market acceleration. These technologies enable the industry to address the challenges posed by the limitations of traditional scaling, enhancing system capabilities and performance in various applications, including high-performance computing, artificial intelligence, 5G communications, automotive electronics, and healthcare devices. An overview of these three core HI platforms will be presented along with applications areas.

In recent year, based on high performance computing (HPC) and big data computing (BDC) application need to upgrade these performance incudes high process rates, high communication rate and low latencies. As transistor scaling reaches physical and economic barriers, the performance and cost of transistors are increasingly lagging behind the historical Moore's Law trajectory. Heterogeneous integration of SiP (system in package), 2.5D and fan-out solutions are driving the beyond Moore vision. In this paper, it is demonstrated that one of fan-out technology is to provide the high RDL layer count and fine RDL line width and line space, called FO-MCM (fan-out multi-chip modules). The FOMCM used organic interposer is applied lower RC delay and the high I/O density interconnection for HBM dies integration in comparison to 2.5D with the whole piece of Si interposer. Since HPC and BDC application performance derived High Bandwidth Memory grow up, that also impact the assembly package structure in parallel. The next general HBM need more metal layers to keep the performance in high frequency compare to original package design. SPIL's FO-MCM development integrates chips by 1 ASIC die and 2 HBM with 4–6 layers RDL show in Fig. 1. Since FOMCM used organic interposer to bridge chips, this kind of package can provide the solution which is cheaper than 2.5D and has simply vendor management to the end customer. As such, an overview of Fan-out integration solution associated with HBM will be presented in this paper.

Package on Package (PoP) technology can play a vital role in advanced packaging for various reasons. The use of a thin interposer allows for tighter wiring ground rules and can reduce die-to-die latency when placing either multiple die on a single interposer or placing multiple interposers on a larger carrier laminate. This assembly technology can also be of benefit for heterogeneous integration applications. The main challenge for bond and assembly process development with organic to silicon bonding, particularly with thin organic interposers, is to overcome solder join defects (non-wets, bridges) created by highly warped components. To address this issue, two different assembly process flows were developed, namely process A (chip first) and process B (laminate first) with PoP type test vehicle hardware. The assembly was composed of a 23×29mm die with 185μm pitch SAC solder connected to an organic interposer of 37.5×37.5mm dimension and 0.7mm thickness. The bottom side of the interposer, with either CuOSP or NiPdAu pads, was soldered to a 68.5×68.5mm carrier laminate of 1.8mm thickness and CuOSP pads with SAC 305 μBGA solder balls of 0.4mm pitch. To ensure bond and assembly integrity, over 30 cross-sections were performed on the modules from these two process sequences. μBGA's were of first interest as warpage issues forced a thorough optimisation of joining parameters. Microstructure appears with undeniable variations between process sequences and interposer pad surface finishes. Cross-polarized microscopy observation and etching of cross-sections, with over 2500 μBGA characterized, showed that process flow A microstructure was mostly constituted by very large and few grains of beta-Sn phase compared to mainly small interlaced grains for process flow B. IMC's with "chip first" (process flow A) assembly were composed of rare AgSn crystals and several CuSn filaments, which were also observed on "laminate first" (process flow B), but only with NiPdAu interposer pads. Also, for process sequence B with NiPdAu pads, thick plates of AgSn were observed, as opposed to very thin sheets with CuOSP pads. Interim cross-section in the bond and assembly process flows allowed the formulation and verification of a hypothesis on the mechanism that leads to a "laminate first" atypical microstructure. Cooling rates during reflow and interposer pad surface finish will change all the kinetics of intermetallic nucleation and produce eccentric growth. A thorough mechanism understanding will allow a proper process parameter intervention to modulate a desired microstructure from a reliability stand point.

Low-temperature solderless Cu-Cu bonding is an important technology for advanced packaging, such as fine-pitch 3-D packaging and heterogeneous integration. In this study, we prepared an oxidation-free Cu surface using an optimized N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma process in a two-step Ar/N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma treatment based on the design of the experiment method, to improve direct Cu-Cu bonding quality at 260 °C. The N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma treatment process was optimized using the Minitab optimizer with chemical state results obtained by X-ray photoelectron spectroscopy (XPS) analysis. The Cu surface treated under the two-step Ar/N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma with optimized N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma conditions not only formed Cu nitride well, but the surface remained without further oxidation for at least one week at room temperature. The Cu-Cu bonding was performed at the low bonding temperature of 260 °C and low bonding pressure of 0.9 MPa for 1 hour, and the bonded interface was evaluated using scanning acoustic tomography (SAT) and field emission scanning electron microscope (FE-SEM) images. We measured shear strength to estimate the bonding interface quality of the oxidation-free Cu-Cu bonding specimen. A maximum shear strength of 62.6 MPa was obtained. Our bonding results demonstrated remarkably improved Cu-Cu bonding quality compared with other previous Cu-Cu joint studies that used Sn, Cu/Ag nanoparticles, or Cu composites.

The line between packaging and silicon interconnect technology is blurring due to a reduction in package interconnect dimensions, which drives an increase in image resolution requirements. It is becoming more difficult to localize and image defects and structures throughout the packaging life cycle, from materials selection, through package and silicon design co-optimization, development, production, and field failure diagnostics. Characterization and failure analysis (FA) solutions must provide fast results for rapid development of packages meeting the required electrical, mechanical and reliability specifications with high yield and quality. Heterogeneous integration and complex packages containing multiple die drive new approaches to rapidly characterize structures, defects and processes. This paper presents new artificial intelligence (AI) developments in 3D X-ray microscopy (XRM) for non-destructive submicron-resolution imaging of packages. It also introduces the latest developments in focused ion beam (FIB) microscopes adapted with an integrated fs-laser for precise and fast analysis of deeply buried features in advanced packages.

For the purpose of increasing the integrated density of electronic system, the multi-chip packaging (MCP) technology has become important and popular [1]. Toward the specific application, there are a variety of commercialized proprietary MCP models in the market. This paper describes the MCP technology for extending the capacity of the memory application from 64Mb Synchronized Dynamic Random Access Memory (SDRAM) to 128Mb SDRAM assembled in the TSOP-II 54L package. The package design concept and mold- flow modeling are summarized with the manufacturing process flow of the package. Two chips are bonded in this package in parallel rather than stacked together with a BT substrate as the interposer for electrically interconnecting the signals among the chips and the outer I/O pins. In addition to the new processes for substrate handling, the modification of process parameters is negligible against to current TSOP II 54L processing flow. Reliability properties are evaluated for the package. It reveals that Moisture Sensitivity Level (MSL) performance could exceed the JEDEC level 3 requirement. The package integrity is proven after 300 cycles Temperature Cycles Tests (TCT). Others environmental evaluations give positive results.

In an age of evolving communication standards like 6G and inevitable disruptive technologies spawned by AI, it is necessary to have the flexibility to apply the best semiconductor technologies to meet application requirements. No single technology will deliver the bandwidth, power, and energy efficiency requirements of emerging applications. Combining multiple chiplets like advanced CMOS and III-V requires heterogeneous integration. The Florida semiconductor ecosystem is uniquely positioned to this essential flexibility to solution providers. For example, silicon interposers can be manufactured at NeoCity that combine Damascene BEOL Cu, embedded passives, high aspect thru Silicon vias (TSV), and low-loss interconnect layers. Chiplets integrated on this platform can deliver high bandwidth with minimal power consumption. This presentation will summarize the ongoing work sponsored by the NSF Florida Semiconductor Engine to build the co-design infrastructure required to enable moving designs from R&amp;D concepts to prototypes and demonstration subsystems. These applications are a significant focus area of imec globally with special emphasis on opportunities to grow the market in the US. Anyone tackling challenges created by higher bandwidth requirements should consider attending.

Advanced heterogeneous integration (HI) technology is much needed for applications from edge to cloud to meet the stringent system-level requirements on performance, power, profile, cycle-time and cost (P3C2). In addition to 3DIC with TSV innovative packaging technologies such as silicon interposer (2.5D) and fan-out wafer-level-packaging (2D/3D) become new paradigm for the semiconductor industry to realize the system integration. In this paper, we will discuss the new trend of advanced packaging technology — a strong need for application-specific integration solutions. Many of those are proposed. The solution with higher performance at lower cost will prevail. Furthermore, the solutions that readily integrate multi-chip to enable chip-partition to extend Moore's Law effectively have long-term advantages.