Development of 3D Stack Package Using Silicon Interposer for High Power Application

In recent years, 2.3D packages using organic substrate are remarkable attention as a next generation high-end packages that realize to high speed and large-capacity computing system. i-THOP® (integrated-Thin film High density Organic Package) which is 2.3D type package, was developed. iTHOP® has structure in which organic interposer is stacked on build-up substrate. Transient Liquid Phase (TLP) technique using Sn-Bi solder has been employed for solder joints between organic interposer and build-up substrate. It is possible to raise the melting point by consuming the Sn phase in the solder to form the Cu-Sn inter-metallic compounds (IMCs). In this report, electromigration tests were performed on solder joints between organic interposer and build-up substrate. And the results were compared with the results of electro-migration test of the flip chip joints using Cu pillar / Sn-Bi solder. The current density was applied 38k A/cm2 at 125 degrees C. The resistance has rapidly increased to 4 % at 30 hours. And the resistance has slowly decreased to 0% at 1000 hours. Open failure was not observed at 1000 hours. Regarding to after assembly, Bi, Cu3Sn, Cu6Sn5 phase were observed at the solder joints between organic interposer and build-up substrate. Almost of Sn phase is consumed to form Cu- Sn IMCs. After electro-migration test, no segregation of Bi layer that caused an increase in resistance was observed. On the other hand, in the case of the flip chip joints using Cu pillar/Sn-Bi solder, the resistance has rapidly increased to 46 % at 100 hours. After that, the resistance has gently increased to 83 % at 2200 hours. And then, the resistance has slowly decreased to72% at 4840 hours. Bi atoms quickly migrated to the anode side by the electron flow. After electro-migration test, thick Bi layer was formed at anode interface. The amount of Bi layer formed on the anode side of Sn-Bi solder joints between organic interposer and build-up substrate is smaller than that of flip-chip joints using Cu pillar / Sn-Bi solder. In the case of Sn-Bi solder joints between organic interposer and build-up substrate, stable IMCs can be formed more quickly. These results indicated that applying TLP-like Sn- Bi solder joints between the organic interposer and the build-up substrate was stable.

Recently, 2.5D package structure such as using silicon interposer is used for high end sever and HPC (High Performance Computing) with high density connection between logic device and memory device. We are developing high density organic package called i-THOP® (integrated-Thin film High density Organic Package) 2.3D type combining organic interposer and build-up substrate. The organic interposer was mounted on build-up substrate. Interconnection between organic interposer and build-up substrate was consisted of copper post and Sn-Bi solder. The bonding process was applied by using the pre-applied NCF (Non-Conductive Film) method. Interconnection was achieved under 200 degrees C by using Sn-Bi solder. The good wettability of Sn-Bi solder was observed at joint portion with minimum 200 μm pitch and no NCF void was confirmed by SAT (Scanning Acoustic Tomography). After that, die assembly was evaluated. The good wettability of solder joints of assembled small die and large die was confirmed with minimum 40 μm pitch. Sn-Bi solder joints were also stable without re-melting after die assembly and stiffener attach process. The thermal warpages of i-THOP® 2.3D type was measured after organic interposer stacking, die assembly and stiffener attach. The warpage without die was small at approximately 20 μm at 30 degrees C and almost no change from 30 degrees C to 250 degrees C. However, the warpage with die was large at 300 μm at 30 degrees C. After stiffener attach process, the thick stiffener over 2.0 mm could reduce warpage below 200 μm that is the criteria of 1.0 mm pitch BGA (Ball Grid Array). The reliability tests of TC (Temperature Cycling), HTS (High Temperature Storage Life), u-HAST (unbiased-Highly Accelerated Temperature and Humidity Stress Test) and b-HAST (biased-Highly Accelerated Temperature and Humidity Stress Test) were carried out. The criteria of TC 1000cycles, HTS 1000 hours, u-HAST 192 hours and b-HAST 96 hours were passed.

In recent years, tremendous research and attention have been focused on 2.5D/3D IC (integrated circuit) integration within a TSI (Through Silicon Interposer) package. Integration of multiple ICs with the use of TSI technology could bring about higher integration density, shorter interconnection path and smaller device structure for the next-generation semiconductor devices. In this paper, we investigated the warpage behavior of our Chip-on-Chip-on-Substrate (CoC)-oS TSI package using the Chip-on-Chip (CoC) first assembly approach. The C4 (controlled collapse chip connection) bumps on the CoC TSI package was attached using both flux-based ball drop process and laser solder ball jetting process. Warpage analysis and profile for each assembly part/package in the CoC-first assembly was measured using the shadow moire method. Two guest dies were assembled onto a large (38.70mm × 26.70mm) and thin (0.10mm) TSI package using flip-chip thermo-compression bonding. The assembled CoC TSI package was then mounted onto an organic substrate. Warpage measurement was conducted from a temperature range of 25°C to 250°C. From the shadow moire measurement results, the warpage difference between the organic substrate and the assembled CoC TSI package with C4 bumps via laser solder ball jetting process is much smaller than using the ball drop process, at room temperature during the initial package placement prior to the reflow process. High warpage difference between the organic substrate and the assembled CoC TSI package with C4 bumps would result in opened and stretched solder joint interconnections issues, especially around the edges and peripheral of the package. Opened solder joint would result in no electrical connection and stretched solder joint would increase the risk of solder joint breakage and affect the long-term reliability of the package. Hence, the initial warpage difference between the assembled package and organic substrate during the assembly process can induce significant effects. In summary, we have demonstrated that the assembly process with the use of laser solder ball jetting process would reduce the warpage of CoC TSI package with C4 bumps, thus reduce the warpage difference with the organic substrate. Hence, the reduction in warpage of the assembled CoC TSI package can improve the process control of the CoC-first assembly flow.

3D chip stacking with through silicon vias (TSVs) has been identified as one of the major technologies for achieving higher silicon packaging density and shorter interconnect. The test vehicle presented in this paper is a 3D chip stack package. Each layer of the test vehicle has two silicon flip chips mounted at the bottom of a silicon interposer with solder bumps. The flip chip has the equivalent dimensions and pad patterns as commercial memory chips. The interposer, with multiple interconnect TSVs for electrical connection and a central TSV for underfill dispensing, can function as a logic chip or as a redistribution chip in a real application. The assembly steps of the test vehicle include conductive adhesive filling for the interconnect TSVs, bonding two bumped flip chips on an interposer (to form a single layer), vertical stacking of the single layers and underfill dispensing. For the filling of the interconnect TSVs, an auger-dispensing method is first adopted to overfill the interconnect TSVs, followed by removing the excessive adhesive beyond the interconnect TSVs by squeegeeing. A jet valve continuously dispenses free dots of an underfill encapsulant into the central TSVs. The central TSVs function as an entrance for underfill dispensing and an uninterrupted point-source to provide fluid for each layer. The free dots form a capillary flow to fill the under-chip spaces of the test vehicle. The usage of TSVs rather than chip edges eliminates the presence of a wide edge reservoir, resulting in smaller ‘keep-out’ area occupation on the substrate.

The rapid advancement of artificial intelligence (AI) has propelled the demand for high-performance computing (HPC) systems capable of handling vast amounts of data. This necessitates improvements in data processing speed within system-on-chip (SoC) units and efficient data transmission between SoC and high-bandwidth memory (HBM). Advanced packaging solutions, particularly the silicon interposer and organic interposer, have emerged to address these challenges. This article delves into the thermo-mechanical performance of 2.5-D packages with an organic interposer, focusing on warpage management during fabrication and stress analysis induced by coefficient of thermal expansion (CTE) mismatches. The study employs finite element analysis (FEA) modeling to evaluate the impact of various factors on warpage behavior and stress levels. Parametric studies on material selection and interposer geometric design reveal crucial insights. Specifically, reducing bridge die and redistribution layer (RDL) thickness mitigates warpage at the controlled collapse chip connection (C4) level, albeit with adverse effects on BGA level warpage. Material selection significantly influences warpage behavior. Organic materials with higher CTE reduce the mismatch between the interposer and the substrate but it is adverse for the interconnection between chiplets and interposer. Moreover, stress analysis indicates the organic interposer’s effectiveness in reducing interconnection stress compared to silicon interposers. This research contributes valuable insights into the design and optimization of advanced packages with bridges embedded in organic interposers, providing guidelines for material selection and geometric design to enhance reliability and functionality. The findings facilitate the development of advanced packaging solutions capable of meeting the demands of AI-driven applications in challenging operational environments.

As the industry moves forward the age of more than Moore, the next generation of packaging moves forward high density of chiplet or die splitting package integration. Especially for high performance computing applications, the advance packaging is to provide the economic benefits to integrate multiple chiplet dies by silicon or organic interposer. Organic interposer is one of the alternative interface for die to die interconnection. It is well-known by FO-MCM to apply in chiplets integration and ASIC to Serdes dies integration by the homogeneous package integration concept. Due to the motivation of AI computing and HPC market growth, the trend is formed to integrate the packaged HBM into packaging module as the heterogeneous integration package (HIP). Both of the platforms, 2.5D with silicon interposer base and FO-EB with partial bridge die as interconnection media, have already launched to market in recent years. FO-MCM with purely organic interposer, is also discussed to implement into the heterogeneous integration field. The fully organic interposer can provide the flexible design in multiple RDL layers and line / space for HPC products. In this study, it is to address FO-MCM platform with purely organic interposer to implement heterogeneous packaging with integrated HBMs. Chip last approach in FO-MCM has the advantage to control RDL quality and take “known-good RDL” for top die cost rescuing. The fan-out RDL configuration is 4 layers with min, L/S of 2/2um. In the verification processes, based on the simulation analysis, the warpage and stress are optimized by material and under-fill selections in this discussion. The assembly results indicated the warpage and reliability validation passed by MSL4, TCT700x, uHAST96, and HTST1000hrs conditions.

2.5D packaging technology utilizing silicon interposers is being developed and used for high-performance applications as the demand for miniaturization and higher density continues to increase. Silicon interposers enable very high density interconnects using standard semiconductor fabrication process technology, but are challenged as size increases. An alternative solution, high density laminate interposer, can offer advantages in cost, form factor, and infrastructure over other interposer options available today. However, it is difficult to manufacture high density wiring and flip chip bump pads on laminate interposer because conventional build-up technology limits fine line and via diameter. Our solution is the combination of an integrated organic interposer substrate with high density interconnects and thermo-compression flip chip bonding. Our solution eliminates the backside integration process for silicon interposer and assembly of interposers onto substrates. Conventional assembly processes can be utilized for assembling dies onto the integrated organic interposer substrate. Feasibility of this 2.5D package has been demonstrated by assembling dual-die with 40um pitch copper pillar bumps onto this novel integrated organic interposer substrate with 2μm line and space.

The demand of the high storage memory is providing a momentum for stacking technology in DRAM industry. As the stack technology is developed, more heat sources are embedded in the same package footprint and increase the device temperature. Therefore, the thermal management is one of most important issues in DRAM stack package. Since the chip stack and package stack technology are competing each other as a solution of DRAM stack, it is necessary to characterize thermal behavior of each package for better thermal management. Hence, in this paper, the authors studied the thermal performance characteristics of chip stack and package stack package in component and module level. The study is focused on the dual stack, which is most demanded stack height in DRAM market. The test package and module was assembled with the thermal test die and the DRAM junction temperature was measured to compare the thermal performance. The package stack package showed better thermal performance in component level because of its larger package size. On the other hand, the chip stack package showed better thermal performance in module level when the heat sink is used.

Proper thermal design and evaluation of 3D stacked IC packages remain to be a key challenge. This is especially the case if the underneath die in the stacked package is large in size with high power dissipation, which is typical for a processor allocated under the memory stack. In this work, a novel thermal bridge structure is introduced to address the thermal management of stacked die package piled with memory chips on processor, which is then connected to the metal lid and heat sink. The thermal issues associated with the package are highlighted and then the enhanced thermal performance of the present package with thermal bridge is demonstrated through numerical modeling. Numerical results show that both the on-chip temperature and temperature difference can be minimized significantly with the thermal bridge structure. For the bump cases investigated, the case of bump(50,30) provides the lowest processor temperature with the lowest temperature level. Thermal bridge with high thermal conductivity is more favorable at the smallest bump case with the lowest bump thermal resistance. Finally, it is pointed out that there exists an optimal range of thermal resistance ratios, at which the minimum temperature difference can be achieved on the processor.

Semiconductors are running in Moore's beat bringing out impressively small processor, memory, amplifier and sensor chips. However, their packaging is more often the challenge for developers and system designers. The paper describes requirements and solutions for two advancing 3D chip packages. The first application is a request for a magnetic field sensor in the narrow gap between rotor and stator of electric motors under the influence of temperature, axial and radial load. This LTCC multilayer providing twisted pair wiring and stepped cavities including a lowered bond shelf is 200 microns thin. The second one is a challenging package for a space component with a 7 layer stepped cavity. It enables multi level wire bonding to the <50μm pitch of the detector chip. Beside the large chip the package is carrying multiple soldered or adhesive bonded chips and passive components, the flex and a robust LGA connector. Further reasons for the choice of LTCC were stiffness, high reliability expectations and thermos-mechanical matching to silicon under space conditions.

In this study, we developed a Cu paste that can be used as a filling material for through silicon via (TSV), through glass via (TGV), and organic substrates. Non-through holes with diameters ranging between 20 and 100 μm and depths ranging between 70 and 100 μm (aspect ratios from 1 to 3.5) formed in a silicon surface layer were filled with Cu paste. TGV substrates with diameters ranging between 30 and 90 µm and thickness of 300 µm were filled with Cu paste without cracking. Multilayer substrates with the diameters of 180 and 260 µm and a thickness of 6.4 mm (aspect ratios: 25, 36) were filled with Cu paste without cracking. The 2.5D chip package was prepared using a TSV filled with Cu paste as a 2.5D interposer. The 2.5D chip package was verified through reliability test [thermal cycle test (TCT), high temperature storage test (HTST), un-bias high accelerated stress test (HAST) and pressure cooker test (PCT)]. After the reliability test, the conductive resistance of the package that adopted the Cu paste was found to be within 10% of the initial value. Moreover, we found that Cu paste can be applied to 2.5D interposer as filling material.

This contribution describes modelling and technology for an Ultra-Thin Chip Package (UTCP), based on the embedding of ultrathin dies in flexible substrates. Chips with thickness in the range of 20 - 30 μm are packaged in between 2 polyimide layers. The result is a very thin chip package, with a total thickness of only 50 - 60 μm. Chip, PI layers and metal are so thin that the whole package is bendable. The base substrate is a uniform polyimide layer, applied (spin coated and cured) on a rigid carrier. Then the ultrathin chip is placed and fixed, using BCB as die attach material. Next, the second spin-on polyimide layer is applied and cured. Vias to the contacts of the chip are laser drilled and the contact metal layer is sputtered and photolithographically patterned. This metal layer is providing a fan out to the contacts of the chips. Finally the whole package is released from the rigid substrate. The resulting package can be SMD assembled on PCB or flex, or can be embedded in a stack of PCB layers, replacing for example the naked die - with the advantage that alignment constraints for the embedded package are not as severe as for the embedded die. Also the “Known Good Die” (KGD) issue is solved as the packaged chip can be tested before embedding. UTCP's have also the potential for stacking in order to obtain 3D type chip packages.

Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a small form factor for a variety of applications. In this work, conventional C4 (controlled-collapse chip connection) technology is studied for robust interconnection between stacked thin chips. Various solder hierarchies to enable 3D chip stacking and packaging are investigated. Examples are presented to compare stacking schemes with sequential and parallel reflow. Chips as thin as 90 µm are stacked using conventional chip-placement and reflow processes, and the associated process challenges are investigated and discussed. Warpage of the thin chips is measured on various substrates. Rework of the chip stack has also been demonstrated through a temporary chip attachment operation, and the scalability of reworkable C4 is investigated.

III-Nitrides promise to offer high-frequency power amplifiers at higher power densities. This is attractive for realizing device platforms for 5G and beyond. It also enables integrating Si-based electronics to complement functionalities. However, to obtain the full potential of III-Nitrides one must operate these transistors at higher power densities, for which thermal management is crucial.Due to the continuous need for higher performance in various applications ranging from DC to W-band frequencies, semiconductor devices are pushed to higher power densities. This results in a higher junction temperature owing to the Joule heating in the channel resulting in device performance degradation and premature failure. Using devices based on wide-bandgap (WBG) semiconductors such as Gallium Nitride (GaN) and Gallium Oxide (GaOx) with a larger critical electric field and high-temperature tolerance, one could increase the power density. However, in order to increase the output power to the levels that is promised by these wide bandgap materials, junction temperature reduction through device-level cooling is critical. We are actively researching thermal management at device, circuit and packaging level using synthetic polycrystalline (PC) diamond. PC-diamond, at an appropriate grain size offers a TC is higher than any competing thermal vias with metals without interfering the electrical performance. Over the past 5 years we have demonstrated the potential of integrating diamond with GaN and recently achieving a record low diamond/GaN thermal boundary resistance (TBR) along with a relatively high diamond thermal conductivity (TC). This remarkable thermal performance was be achieved by maintaining the electrical performance, as demonstrated by the unharmed channel charge and mobility results.There are two key requirements for thermal management using heat spreading from the channel: first, a low thermal boundary resistance (TBR) between the hot spot in the channel and the heat spreader is required (in this study between GaN channel and diamond). Second, a low thermal resistance path to the heat-sink is crucial from the diamond layer which is directly proportional to diamond’s thermal conductivity (TC). In collaboration with Univ of Bristol, we have reported a TBR of ~3 m2K/GW, to date, known to be the lowest reported TBR for GaN HEMT technology. Diamond-GaN TBR depends strongly on the interface smoothness and the thickness of interfacial Si3N4 layer. A thinner Si3N4 resulted in lower TBR and allowed superior phonon coupling from the channel to the spreader. We have also measured a remarkably high TC for a 2 μm-thick diamond layer yielding over 650 W/m.K. The diamond grains are near isotropic in shape that allows excellent in-plane and cross-plane thermal conductivity. Achieving high TC within a thin film of diamond, grown heterogeneously, underscores the importance of our technique, since it reduces the residual stress when integrating with different materials that involves many thin layers like GaN/AlGaN HEMT epi-layers.β-Ga2O3 is an emerging ultra-wide bandgap material showing promises for both power and RF devices. However, the material’s low thermal conductivity poses to be a challenge for efficient power delivery (at any frequencies). PC diamond was successfully grown on (‾¯201)β-Ga2O3 using proper nucleation technique and thermal characterizations were conducted. A thermal conductivity (diamond + nucleation) and thermal boundary resistance at the diamond/β-Ga2O3 interface of 110 ± 33 W/mK and 30.2 ± 1.8 m2K/GW, respectively were measured.Our current results demonstrates a very promising roadmap for wide bandgap semiconductors via diamond integration.

The most singular focus of the electronics industry during the last 50 years has been to miniaturize ICs by miniaturization of transistors and on-chip interconnections. Two major problems are foreseen with this approach; (1) electrical leakage and (2) the lack of improved electrical performance beyond 16nm. As a result, the industry is transitioning from the current SOC-based approach to a through-silicon-via (TSV) based 3D IC-stacked approach. However, a major challenge remains; these 3D ICs need to be interconnected to other ICs with a much higher number of I/Os than are available with current ceramic or organic interposers. While silicon interposers currently in development can provide these high I/Os, they cannot do so at low enough cost. In this extended abstract, 3D Glass Solutions, a division of Life BioScience, Inc., presents our efforts in glass interposer microfabrication. Glass interposers possess many advantages over silicon interposers including: cost, production time, and scale. 3D Glass Solution’s APEX™ Glass ceramic is a photo-sensitive material used to create high density arrays of through glass vias (TGVs) using three simple processing steps: exposure, baking, and etching. To date, we have been successful in producing large arrays of 12 micron diameter TGVs, with 14 micron center-to-center pitch, in 125 micron thick APEX™ Glass ceramic. This extended abstract covers (1) on our efforts producing high aspect ratio TGVs in ultra thin (75–250 micron) APEX™ Glass ceramic wafers, (2) maximum TGV aspect ratios, and (3) TGV fidelity and limits of manufacturing.