Advancing Packaging Solutions Using 3D Capabilities of Ceramic Multilayers

Stacking of many functional chips in a 3D stack package leads to high heat dissipation. Therefore a new platform technology is required to assemble chips vertically and remove the heat effectively. A 3D stacked package with silicon interposers is developed to integrate one ASIC and two memory chips in a package. Electrical connections in the silicon interposer are formed by through silicon via. Silicon has much high thermal conductivity than organic interposers, which reduces drastically the package thermal resistance. Thermal performances of the 3D package are analyzed and thermal enhancement methods like thermal vias, thermal bridging are evaluated. The designed package is having 5 times lesser thermal resistance compared to the package with organic substrate. An additional silicon heat spreader is attached to the package for high power application. Numerical analysis and experimental validation are carried out. The designed 3D stack package is found suitable for 20 watts heat dissipation

With the latest gaming systems such as X-box, Playstation 3, PSP, IPTV, and H264 requiring more bandwidth, packaged in smaller devices, and providing higher quality, in return they evacuate more heat and consume more power, thus making power consumption and thermal dissipation a major issue for chip designers in the nanometer era.Thermal effects on the chip and package is the next wave. First, there was signal integrity. Then power integrity and now, there is a new first-order effect in the horizon for IC and system designers called thermal integrity. And the traditional design methodology of using uniform temperature across the chip is becoming woefully inadequate and provides insufficient data to the package and system designers, unable to meet the requirement and demands of the consumer. To better understand the impact of temperature variation on chip's performance, both power distribution and package characteristics must be considered in the design and analysis flow. Likewise, a realistic view of the heat distribution across the chip is becoming essential for package and system designers. What makes the analysis of signal, power, and thermal integrity effects challenging is that they must all be considered concurrently across the entire chip, which requires novel approaches to mitigate the issue.The panel will discuss how urgent is the impact of thermal integrity on system designs and is this a real concern or are we making it up?When and under what condition will it become urgent, and is it related to process nodes, low power applications, type of packaging used, etc.? Is there specific design techniques used for more specific multimedia processing? Can you separate the IC design from package and system designs with some assumptions or is co-design the only way? How accurate is the industry's understanding of the physics of the chip (device), interconnect, and package? Is thermal integrity a first order or second order effect?Given the other variations from nominal, how important is this.The moderator will conclude with a summary of the panelist comments and be able to make a forward-looking statement about the future of power and heat and their impact on system design.

This contribution describes modelling and technology for an Ultra-Thin Chip Package (UTCP), based on the embedding of ultrathin dies in flexible substrates. Chips with thickness in the range of 20 - 30 μm are packaged in between 2 polyimide layers. The result is a very thin chip package, with a total thickness of only 50 - 60 μm. Chip, PI layers and metal are so thin that the whole package is bendable. The base substrate is a uniform polyimide layer, applied (spin coated and cured) on a rigid carrier. Then the ultrathin chip is placed and fixed, using BCB as die attach material. Next, the second spin-on polyimide layer is applied and cured. Vias to the contacts of the chip are laser drilled and the contact metal layer is sputtered and photolithographically patterned. This metal layer is providing a fan out to the contacts of the chips. Finally the whole package is released from the rigid substrate. The resulting package can be SMD assembled on PCB or flex, or can be embedded in a stack of PCB layers, replacing for example the naked die - with the advantage that alignment constraints for the embedded package are not as severe as for the embedded die. Also the “Known Good Die” (KGD) issue is solved as the packaged chip can be tested before embedding. UTCP's have also the potential for stacking in order to obtain 3D type chip packages.

Miniaturization is an essential requirement for development of space-borne electronics hardware. Recently, advancements in the device and packaging technology such as Analog Front End (AFE), FPGA and ASIC has enabled on-board designers to develop space worthy, high reliability miniaturized hardware meeting the functional and performance requirements. HMC, SIP, 3D packaging technology etc. can further miniaturize the hardware by embedding dice, devices, active and passive components. 3D packaging technology, which is ESA qualified, allows us to integrate packaged devices and printed circuit boards (PCB) with high reliability vertical interconnections. It is possible to migrate from existing PCB designs along with the same bill of material to 3D packaging technology. A development of miniaturized camera module consisting of 4K elements linear detector, detector drive electronics, analog video processing and digitizing electronics, timing and control logic along with serial data output has been carried out for space use using 3D packaging. Brief details of this camera hardware, development steps and realization challenges along with test results are given in this paper.

Technical analysis of intellectual property (IP) is conducted for the purpose of legal protection and product development. A brief review of the process of IP analysis and associated terminology is...

A miniaturized implantable multi-sensor system for cardiovascular monitoring of physiological parameters is presented. High accuracy pressure measurements within the vessel can be performed by a capacitive pressure sensor. Additional information about the patient, e. g., sudden movement, inclination or increased temperature can be obtained by additional sensor components such as an acceleration sensor and a temperature sensor unit. This information facilitates compensation of interferences for more accurate pressure measurements. A multi-functional ASIC enables, amongst others, sensor signal processing, power management and telemetric communication with extracorporeal electronics. Sensor chips, the multi-functional ASIC and passive components are assembled on a LTCC circuit board in which an antenna coil is integrated for telemetric energy and data transmission at a frequency of 13.56 MHz. In order to support further miniaturization, the implant shall be encapsulated with a stack of very thin and hermetic ceramics applied by ALD instead of using bulky metal housings. Further encapsulation with polymers, which can be functionalised with appropriate biomolecules, is necessary for a proper shape, a biocompatible interface to the surrounding tissue and, thereby, reduction of thrombogenicity.

The stretchable sensor skin we propose uses microwaves propagating in a two-Dimensional Signal Transmission (2DST) sheet. A small tactile sensor chip with a pair of Resonant Proximity Connectors (RPCs) couples with 2D microwaves carrying signals. Chip operating power is also supplied by 2D microwaves. The RPC is a spiral electrode whose arc length is a quarter of the electromagnetic wavelength. Chip operating power is supplied by 2D microwaves. Sensor chips are connected to the 2DST sheet by RPCs without electrical contacts anywhere on the sheet. Resonance induced at the electrode reduces impedance between the connector and the conductive layer of the 2DST sheet, enabling sensor chips to be connected stably to the sheet. Experimental results on the RPC show the concept to be effective. We fabricated a 1-bit (touch detection) tactile sensor element consisting of a RFID-tag and RPCs, and confirmed in experiments that the sensor element operates in a stretchable 2DST sheet.

A theory is constructed of the temperature dependence of quantum oscillation phenomena in narrow-gap electronic semiconductors, taking into account the thermal smearing of Landau levels. Oscillations of longitudinal electrical conductivity in narrow-gap electronic semiconductors at various temperatures are studied. An integral expression is obtained for the longitudinal conductivity in narrow-gap electronic semiconductors, taking into account the diffuse broadening of the Landau levels. A formula is obtained for the dependence of the oscillations of longitudinal electrical conductivity on the band gap of narrow-gap semiconductors. The calculation results are compared with experimental data.

Telecommunication equipment that supports high-level information networks is being made portable, small and lightweight. Thus, the miniaturization of semiconductor devices is necessary, and chip thinning technologies are important key technologies to achieve it. The manufacturing steps for semiconductor devices are generally classified into steps for patterning semiconductor elements in a wafer, steps for thinning a wafer, steps for dicing semiconductor elements into chips and sealing the chips in packages. Wafers are thinned by means of mechanical in-feed grinding using a grindstone containing diamond particles, resulting in spiral grinding saw marks on the backside of the wafers. Dicing wafers always causes surface chipping, dicing saw marks on the chip side and backside chipping. Such defects on chip faces become sources of cracks, decreasing chip strength. Therefore, the manufacturing process of thin chips must achieve the requirement of no damage on all chip faces. We already proposed a novel wafer thinning process namely a dicing before grinding (DBG) and DBG + mirror finish process on 56 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> ECTC [1], and also proposed a novel flip chip process for ultra thin chip on 57 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> ECTC [2]. Incidentally, the thickness required for a semiconductor chip to work has not yet been determined. In this paper, the memory chip performance test results are described.

3D Packaging Technologies and Applications, Latest Challenges and Supply Chain ActivitiesSemiconductor industry, for more than four decades, has rigorously followed Moore's Law in scaling down the CMOS technologies. Although several new materials and processes are being developed to address the challenges of future technology nodes, in the coming years they will be limited with respect to functionalities that future devices will require. As a consequence a clear trend of moving from CMOS to package and system architecture can be observed. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect is one the emerging options, considered today the most advanced technology, that could enable various heterogeneous integration. 3D Integration is not limited to the CMOS scaling in itself, it is rather based on bringing more functionalities by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive components) while reducing the form factor of the packaging. This functional diversification is also known as More-than-Moore. In addition, considering Known Good Die approach, each component of the 3D package could have a different manufacturer using different wafer sizes and node technology, thus bringing more complexity but also more opportunities and responsibilities to the supply chain. There are several business models identified, either using vertical integration or collaborative approach, if a dominant one will emerge or several tactics will co-exist, it is still remains a key question that will have to be answered. The supply chain interaction and key players will be addressed in this presentation, including current and future standardization needs. This is today a key for the manufacturing of advanced 3D devices. 3D integration is considered today a new paradigm for the semiconductor industry, since it will drive evolution for packages for the coming decades. Due to several advantages that TSV technology can bring, several platforms have started. 3D WLCSP, 2.5D interposers & 3DIC are the main platforms that will be studied in this paper. Market forecasts in terms of wafer starts, market revenue, segments and end-products as well as supply chain activities and major player interactions will be presented. The industry has enthusiastically been waiting for mass production of 3D ICs. Although some small level of production has already been reported, the adoption rate in high volume manufacturing (HVM) is still low due to unresolved challenges that the industry still needs to address. Process technology is not fully mature, there are still many challenges in bonding and de-bonding, testing as well as thermal management that have to be overcome. Furthermore, design tools have to be fully released to enable proper 3D integration design. Looking at the time to market it is foreseen that device such as the Hybrid Memory Cube, combining high-speed logic with multiple stacks of TSV bonded memories, will come into high volume production in 2014. This will definitely change the world of the memory market and will significantly speed up the adoption of 3D technologies. Technology roadmaps for 3D integration will also be included in the manuscript and reviewed during the presentation.

Encapsulant material for molded underfill (MUF) is widely applied to flip chip type semiconductor packages for mobile applications like as smart phone. Along with high functionality of the semiconductor device, the number of copper pillar for electric contact between die and organic substrate interposer is increasing and the gap between pillars / die and substrate is reducing. As a result of this trend, unfill of encapsurant material between die and substrate becomes more difficult issue. Unfill causes electrical failure during mounting process. For the reason, higher filling ability is required to the encapsulant material. On the other hand, reducing package warpage is important function required for the material. Because large warpage during mounting process causes failure of solder connection between package and mounting board. Behavior of warpage depends on the package structure. Recent trend of thin and coreless substrate adoption, warpage control has become more difficult challenge. In this seminor, we will report the development of advanced encapsulant material for MUF to achieve both filling narrow gap and reducing package warpage. Encapsulant material is composed by epoxy resin, hardener, catalyst, fused silica as filler and other some minor components including coupling agent, releasing agent, pigment and additives. In molding process, it is heated up in the mold die which is kept around 175 degree C and melted, after that filled into narrow gap between die and substrate. While filling, large size filler particles prevent flowing in narrow gap. However, reducing size of filler usually causes reducing flow length because specific surface area of filler increased. These cause worse filling ability. On the other hand, to reduce warpage it is needed to optimize physical properties. To reduce fluctuation of warpage during reflow mounting process, to reduce fluctuation of CTE at high temperature is effective. To reduce fluctuation of CTE, to increase filler content is one of the major method, but it causes reducing flow length and worse filing ability too. For these reasons, we studied the design of encapsulat material to achieve high flow length with small filler size and low CTE fluctuation. We examined the material the fine-pitch flip-chip packages which gap between die and substrate is below 30 microns to the target. Maximum size and size distribution of silica affect to filling ability to narrow gap and flow parameters like as spiral flow and viscosity. We studied effect of silica size to flow parameters and filling ability. After that we optimized the silica design using a maximum particle size of 10 microns. Furthermore we studied composition of resin, latent catalyst and additives to keep low viscosity during filling by controlling cure reaction and achieve good narrow gap filling ability. We developed encapsulant material for MUF applicable to very high pin count, fine pitch and narrow gap flip chip package with low warpage fluctuation by the techniques based on these studies.

Biosensors’ research filed has clearly been changing towards the production of multifunctional and innovative design concepts to address the needs related with sensitivity and selectivity of the devices. More recently, waveguide biosensors, that do not require any label procedure to detect biomolecules adsorbed on its surface, have been pointed out as one of the most promising technologies for the production of biosensing devices with enhanced performance. Moreover the combination of optical and electrochemical measurements through the integration of transparent and conducting oxides in the multilayer structures can greatly enhance the biosensors’ sensitivity. Furthermore, the integration of polymeric substrates may bring powerful advantages in comparison with silicon based ones. The biosensors will have a lower production costs being possible to disposable them after use (“one use sensor chip”). This research work represents a preliminary study about the influence of substrate temperature on the overall properties of ITO thin films deposited by DC magnetron sputtering onto 0,5 mm thick PMMA sheets.

Online and distance education presents many challenges for both educators and system designers. The nature of these challenges is given particular clarity when examining online education in respect to pedagogical approaches which emphasize the importance of dialogue as part of the educational process. In order to begin to understand the dialogic role that technology plays in online education, a phenomenologically-oriented conceptual framework is sketched out. Taking computer interactions to be structured largely as interpretive processes that occur within a wider cultural context, the role of online educational systems in instructor-student dialogue is presented as a form of technological utterance, able to both sustain, as well as instantiate, messages in a dialogue between students and instructors. Introducing questions for future research, the aim is to develop design theory for both the design of online education as well as for design in general.

This paper shows how to use silicon pressure sensors for high temperature and silicon corrosive environments. A sensor chip has been developed to be used in high temperature up to 300/spl deg/C, which has SOI (Silicon On Insulator) structure employing Si/Al/sub 2/O/sub 3//Si double hetero-epitaxial technology[1]. The sensor chip is covered with a stainless diaphragm, and never contact with media of pressure. In experiments, a pressure sensor which is designed for a range of 1 MPa has a sensitivity of 18.3 mV/V/MPa. After compensating of the temperature influence, a maximum offset error of 1.3%F.S., and a maximum sensitivity error of 1.1%F.S. from 50/spl deg/C to 200/spl deg/C were obtained.

In addition to quality electronic components and subsystems, highly reliable interconnects are imperative in high-reliability applications such as spacecraft and satellites. System designers must therefore address and resolve issues related to the proper design and assembly process for connectors and interconnects for passive and active components. We have developed guidelines for the design of a space-qualifiable connector system based on our experience with defective hybrid couplers and power dividers, as well as our understanding of the material properties of the connector dielectric. We also discuss testing and the qualification of vendors of connectors and interconnects necessary to ensure high-reliability radio frequency and microwave components.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>