Aswitched‐capacitorbased multilevel inverter with reduced circuit components and voltage boosting capability

Optimum structure of a generalized three-phase reduced switch multilevel inverter

Most of the asymmetrical reduced-component multi-level inverters (MLIs) can generate their maximum possible voltage levels; however, their total standing voltage (TSV) is comparatively higher. Here, a single-phase, multi-unit MLI configuration is proposed that can generate a maximum number of output voltage levels using minimum components and achieve lower TSV. Here, a single-phase generalized MLI unit is proposed to generate a more number of output voltage levels using lesser components and to achieve lower TSV. The inverter is further extended to a cascaded multi-unit MLI for high power applications. Further, a most optimal generalized multi-unit MLI is derived from the generalized topology that has designed with a minimum component and TSV for maximum voltage levels. The performance of the proposed MLI is compared with other similar existing MLIs in terms of the number of switches, the number of DC sources and TSV with an increase in voltage levels to prove its superiority. Further, a comparative study of voltage stress experienced on the highest voltage rated switches of the proposed most optimal MLI and the most popular CHB trinary is done for an increasing number of levels. The TSV of the proposed 11-level inverter is calculated as 21V DC, which is much smaller as compared to the similar existing topologies. A MATLAB/Simulink based simulation and corresponding experimental results of the 11-level and 47-level inverters are presented at different modulation indices as well as under load variations to verify their effectiveness.

Multilevel inverters (MLI) with reduced components are becoming popular to achieve higher voltage levels with lower cost and complexities of the circuit. Most of the reduced switch MLIs use a large number of isolated voltage sources that have a large total standing voltage (TSV) and higher losses. Moreover, many reduced component MLIs have been developed to reduce the number of switches only and have not utilized the dc-link voltages properly. Thus, an inverter needs to be designed in which the number of dc sources is also small and utilized fully. In this paper, a novel single-phase, multicell MLI configuration is presented that can generate a maximum number of output voltage levels using a minimum number of switches and dc sources. Two optimal configurations of the proposed MLI are proposed based on the minimum requirements of components with the optimum voltage stress of the highest rated switches. Moreover, the TSV of the proposed optimal MLI also becomes low. A generalized multicell optimum MLI is presented and the number of components, voltage stress of all the switches, and the TSV of the proposed as well as the other inverters also determined by the generalized expressions for comparison purpose. The prototype of a specimen 15-level inverter and the optimal 75-level inverter cell is further developed and implemented using DS 1103 in the laboratory to show the effectiveness of the proposed configuration. The experimental results corresponding to the different modulation indices are presented here for the verification of the simulation results.

The utilization of multilevel inverter have been increased since the last decade. These type of inverters get better voltage waveform, and decrease total harmonic distortion (THD). This paper presents the design and simulation of a single-phase asymmetrical multilevel inverter. The inverter can produce a better sinusoidal waveform by increasing the number of output voltage levels. The proposed inverter is capable to generate a nominal asymmetry of 1:2:4:8:16:32 ratio using only six isolated voltage sources. By serial connection of three modified H-bridge modules, it is possible to produce 127 output voltage levels including zero. To verify the performance of the proposed topology, simulation using MATLAB/Simulink is presented. Results show the capability of the proposed topology in reducing device count and satisfied IEEE 519 harmonic standard without using any passive filters while maintaining its performance.

Cascaded H-bridge multilevel inverters shows a useful circuit configuration to increase the number of output voltage levels to obtain high quality output voltage. By applying the concept of the power of three to dc voltage sources, it can increase the number of output voltage levels effectively. To realize this concept, two approaches may be considered. One is to use independent dc voltage sources pre-scaled in the power of three, and the other is to use instantaneous dc voltage sources generated from a cascaded transformer, which has the secondary turn-ratios scaled in the power of three in sequence. A common feature in both approaches is to use the concept of the power of three for dc voltage sources, and a point of difference is whether it adopts a low frequency transformer or not, and where the transformer is located. According to the difference, application areas are limited and show different characteristics on THD of output voltages. We compare and analyze both approaches for their circuit configurations, voltage level generating method, THD characteristics of output voltage, efficiency, application areas, limitations, and other characteristics by experiments using 500 [W] prototypes when they generate a 27-level output voltage.

The multi-level inverters with the reduced components are becoming prevalent because a higher number of output voltage levels can be achieved using a comparatively lesser number of devices. This paper proposes a generalized configuration of single-phase symmetric multi-level inverter (MLI) topology using lesser number of power electronic switches. The comprehensive study of the proposed inverter has been done through a specimen nine-level inverter. Level-shifted pulse width modulation (LS-PWM) technique is applied to produce the corresponding gate pulses. Modeling and simulation of the proposed inverter are done using MATLAB/Simulink. The proposed structure of the nine-level inverter is experimentally executed in the laboratory to validate the simulation outcomes. Moreover, a comparative study of the recommended configuration of the multi-level inverter is done.

A proposed hybrid multilevel inverter topology is derived from the multiple-transformer inverter topology by integrating the flying capacitor asymmetric H-Bridge inverter into the multiple-transformer inverter topology to improve the performance of a multilevel inverter. The Proposed hybrid multilevel inverter topology reduces amount of THD in the output voltage of the multilevel inverter by increasing the number of output voltage levels of the multilevel inverter and reduces the amount of power losses in the power semiconductor switches by using appropriate power semiconductor switches in different switching conditions. The performance of the proposed hybrid multilevel inverter is verified through simulation of the proposed hybrid multilevel inverter topology and comparison of the result from the simulation of the hybrid multilevel inverter topology with the result from the simulation of other multilevel inverter topologies.

This paper proposes a new topology for multilevel inverters based on series and parallel {R1–7} connection’s of the dc voltage sources. Series and parallel {R1–7} connections ability of the proposed topology make it capable of increasing the number of voltage levels and the output current, respectively. The proposed topology is optimized from the viewpoint of number of switches, number of dc voltage sources, and maximum blocked voltage by switches. The optimal topologies with minimum number of switches and dc voltage sources are computed to produce the maximum number of output voltage levels with minimum blocked voltage by switches. In addition, a new algorithm for the determination of magnitudes of dc voltage sources is presented. Furthermore, to verify the theoretical aspects, the proposed topology is compared with some of the new presented multilevel inverters. The performance of the proposed multilevel inverter is verified by the simulation and experimental results of a single-phase 25-level inverter.

Multilevel inverters are very popular in renewable energy applications. These inverters produce output voltages close to sinusoidal and have lower harmonics as compared to the conventional two-level inverters as it also helps in reducing the size of the filter, thus makes the circuitry less complicated. In conventional multilevel inverter topologies, the number of devices increases with the increase of the number of output voltage levels, which in turn makes circuitry bulky and costly. Further, the boosting feature of the input voltage is also necessary for the application of multilevel inverters with renewable energy. Therefore, to reduce the count of devices, losses, and rating of devices, various switched-capacitor multilevel inverter topologies are proposed. Switched-capacitor multilevel inverter topologies (SCMLIs) can generate multiple voltage levels along with high voltage gain with a minimum number of devices. This paper gives a detailed overview of the recently introduced SCMLIs. The different SCMLIs have been categorized based on the number of levels and voltage gains. A detailed comparison has been introduced in this paper. Finally, few SCMLI topologies have been experimentally validated using the experimental results.

In the present paper, single phase multilevel inverter using switched capacitor units is proposed. The switched capacitor unit (SCU) is used in the multilevel inverter will increase the dc supply voltage at the input without using transformer by operating the capacitors in parallel and in series. The SCU comprises one dc source, two semiconductor switches, power diode, and capacitor. The proposed topology does not require the charge balancing operations, which results reducing the cost of the overall circuit. In addition to that, it does not required H-bride module to alter the polarity of the output voltage, which will lead to minimum required semiconductor power switches. The proposed topology is compared with the conventional similar architectures in terms of power semiconductor switches, power diodes, dc power supplies. Finally, to confirm the proposed architecture performance, simulation results are presented.

This work proposes a switching policy for multi-level full-bridge switching power converters and analyses their performance by driving them with a multi-level PWM modulation, targeting high-efficiency power amplifiers. Unlike conventional policies, which generate the output voltage levels only from the values of the supply voltages, this enhanced policy also uses the values of the voltage difference between supply voltages to generate additional output voltage levels, therefore maximising the number of output voltage levels for a given set of supply voltages and connection switches. Simulation results show that, when tracking a band-limited signal, the proposed switching policy can reduce the power of the high-frequency spectral content from 21 % to 11 % by upgrading a 5-level amplifier to a 7-level amplifier without adding supply voltages or connection switches.

It is difficult to make a structure of multilevel inverter for the efficient conversion of dc to ac having a smaller number of power electronic components, less switching losses, less voltage stress on switches, and a greater number of output voltage levels. To breakthrough this problem, a modification is performed in the existing H-bridge multilevel inverter to form a switch ladder modified H-bridge multilevel inverter (SLMHB-MLI). Moreover, for the minimization of maximum voltage rating on the switches and optimization of switching sequence of the multilevel inverter, a novel pulse width modulation (PWM) technique is proposed in this research. Furthermore, in SLMHB-MLI, the novel PWM technique is integrated with an ANDed PWM technique for the variation of output voltage magnitude. The usefulness of the proposed topology and PWM technique are confirmed via comparison with previous topologies simulation and experimentation, respectively.

This paper presents a new single phase H-bridge multilevel inverter topology using reverse-connected voltage source along with a different pulse width modulation (PWM) strategy, to extract a variable frequency variable amplitude output voltage. It involves the use of reduced number of switching devices for a specific number of output voltage levels in comparison with conventional MLIs. Using this configuration, the total harmonic distortion is reduced as total harmonic distortion plays an important role in medium voltage and high power applications for better operation so here with new proposed topology the total harmonic distortion diminishes. In this paper simulation results of the proposed multilevel inverter for a single-phase 7-level multilevel inverter are presented and the total harmonic distortions results of 7, 9, 11-level with different modulation index are shown.

The article presents a comparative analysis of multilevel inverter topologies, emphasizing the number of power components required for each configuration depending on the number of output voltage levels. The most popular topologies are considered, including the diode-clamped multilevel inverter, the flying capacitor inverter, the cascaded H-bridge inverter, and the level-shifted switch topology. It is shown that the level-shifted switch topology requires the minimum number of power components, which reduces implementation costs and makes the design more compact and economically efficient, especially for high voltage levels. The research results may be useful in selecting the optimal multilevel inverter configuration for power consumers that require high-quality output voltage.

A new multilevel inverter (MLI) topology is proposed using a level doubling network (LDN). The LDN takes the form of a half-bridge inverter to almost double the number of output voltage levels. The concept (of the proposed LDN) has the capability of self-balancing during positive and negative cycles without any closed-loop control/algorithm, and it does not consume or supply any power. The topology uses a symmetric cascaded H-bridge MLI but offers an equivalent performance of an asymmetric topology in terms of the number of levels. Also, it maintains the merit of uniform loading of the individual cell for a symmetric MLI. The topology is implemented by connecting only a three-arm H-bridge (only two switches per phase) with the entire three-phase inverter to double the number of levels. Thus, it significantly improves the power quality, reduces the switching frequency, and reduces the cost and size of the power filter. Operation of the circuit is verified by simulation result and experiments from a laboratory prototype.