Auto-Tuning OmpSs-OpenCL Kernels Across GPU Machines

The emergence of accelerator-based computer architectures and programming models makes it challenging to achieve performance portability for large-scale scientific simulation software. In this paper, we focus on a sparse block diagonal matrix multiple vector (SpMM) computational kernel and discuss techniques that can be used to achieve performance portability on NVIDIA and AMD based accelerators using CUDA, HIP, OpenACC, Kokkos. We show that performance portability can vary significantly across programming models, GPU architectures, and problem settings, by up to 52× in the explored problems. Our study visits the performance portability aggregation techniques to guide the development and the selection of performance portable algorithmic variants.

A dynamic microeconomic model is presented that establishes the price and unit sales evolution of heterogeneous goods consisting of successive homogenous product generations. It suggests that for a fast growing supply the mean price of the generations are governed by a logistic decline towards a floor price. It is shown that generations of a heterogeneous good are in mutual competition. Their market shares are therefore governed by a Fisher-Pry law while the total unit sales are governed by the lifecycle dynamics of the good. As a result the absolute unit sales of a generation exhibit a characteristic sales peak consisting of a rapid increase followed by a long tail. The presented approach shows that the evolution of successive product generations can be understood as an evolutionary adaptation process. The applicability of the model is confirmed by a comparison with empirical investigations on successive DRAM generations.

The advancements in modern computer architecture have made it possible for the simulation of large-scale problems that are of industrial application. However, it can be time-intensive to continually port scientific codes to the ever-evolving computer architectures. Therefore, it is important to develop computational tools that make it easy for researchers to port their existing scientific software or develop new software that can run optimally on current and future computer architectures from different vendors. Also, it often advantageous for scientific software to leverage fine-grained parallelism on homogeneous architectures that are comprised of multi-core CPUs and on heterogeneous computer architectures comprised of multi-core CPUs and GPUs. This paper demonstrates the incorporation of performance portability and data-oriented design paradigms in the phase-field modeling of microstructure evolution. To achieve this, we utilized MATAR, a C+ + software library that allows the straightforward creation and usage of multidimensional and multi-size dense or sparse matrix and array data structures that are also portable across disparate architectures using Kokkos. As a case study, we use the phase-field model for spinodal decomposition which numerically solves the Cahn-Hilliard equation using the semi-implicit Fourier spectral method. Performance portability across multi-core CPUs and different GPU architectures are investigated. Additionally, numerical accuracy and performance gains between single and double precision phase-field calculations are investigated.

Accounting for semiconductor industry dynamics

Norton model is a diffusion model to use for a substitution for successive generations of a product. Successive generations of a product influence each other when they diffuse in the same market. In order to express this rules, we try to relax one of the hypothesis of Norton model ,and take the effects of last generations into account Norton model , and define the substitution influence coefficients, then construct the extended Norton model. The extend Norton model improves the explanation of Norton model, and can embody well the actual circumstance of a substitution for successive generations of products. In the end, we take the adoption and substitution for successive generations of the modes of connecting Internet in China as an example for the application of the extended Norton model, and get better results than the Norton model.

It’s hard to investigate the origins of life without having a good idea of what chemical building blocks would have been available. A research team led by and Sara Szymkuć has created a software, Allchemy, that generates networks of potential prebiotic molecules from a handful of simple starting materials ( 2020, DOI: ). The network shows that complex chemistry could have emerged from a basic set of small molecules that were present on early Earth. To create the software, the researchers started with what chemists know about the prebiotic syntheses that were likely possible on our planet before life emerged. Then they fed the program six simple starting materials that were present on early Earth—methane, ammonia, water, hydrogen cyanide, nitrogen gas, and hydrogen sulfide. Allchemy applied the reaction rules iteratively to create successive generations of reaction products connected by a proposed synthetic route. This created a network of hundreds of

This is the final report of a detailed study of the interaction of 670A MeV neon ions with water, used as a presumed tissue-equivalent target. A first comparison of the data with theoretical fluence spectra predicted by the one-generation heavy-ion transport code HZESEC was reported previously. In the present article, subsequent nuclear interactions of the fragment are taken into account, using the LBLBEAM multigeneration heavy-ion transport code, which incorporated new features and modifications intended to address some of the approximations made in the previous calculation. The LBLBEAM code uses the method of characteristics and an iterative procedure to solve a one-dimensional Boltzmann transport equation for the first through third successive generations of nuclear reaction products; it includes a recent version of the semiempirical model used to derive nuclear interaction cross sections. The stopping power used for the theory was calculated in the same way that experimental time-of-flight and energy-loss data are converted to obtain a comparison independent of stopping power; accordingly, good agreement was found between calculated and measured neon fluence spectra in the Bragg peak region. Multiple scattering effects were considered separately for each isotope in the present work. Acceptance factors were calculated as previously, assuming that all projectile fragments originate from the first nuclear interaction. The results show that lower-mass isotopes can account for the high-LET portions of the spectrum in measured fluence spectra. Third-generation products become increasingly important as a source of lighter fragments for depths comparable with the primary particle mean free path, accounting for between one-third and one-half of carbon and lighter particles near the Bragg peak; higher-order interactions were negligible for the detector geometry and material thicknesses examined. Agreement between measured and calculated fluence spectra is 30% (20% for integral fluences). Inclusion of hydrogen, helium, and lithium fragments improves agreement between calculated and measured RBE values for spermatogonial cell survival, but tertiary particle acceptance and track structure effects need to be understood in greater detail to predict RBE accurately.

In this paper, we present the first algorithm for computing threshold ILU factorizations on GPU architectures. The proposed ParILUT-GPU algorithm is based on interleaving parallel fixed-point iterations that approximate the incomplete factors for an existing nonzero pattern with a strategy that dynamically adapts the nonzero pattern to the problem characteristics. This requires the efficient selection of thresholds that separate the values to be dropped from the incomplete factors, and we design a novel selection algorithm tailored towards GPUs. All components of the ParILUT-GPU algorithm make heavy use of the features available in the latest NVIDIA GPU generations, and outperform existing multithreaded CPU implementations.

ARTICo3 is an architecture that permits to dynamically set an arbitrary number of reconfigurable hardware accelerators, each containing a given number of threads fixed at design time according to High Level Synthesis constraints. However, the replication of these modules can be decided at runtime to accelerate kernels by increasing the overall number of threads, add modular redundancy to increase fault tolerance, or any combination of the previous. An execution scheduler is used at kernel invocation to deliver the appropriate data transfers, optimizing memory transactions, and sequencing or parallelizing execution according to the configuration specified by the resource manager of the architecture. The model of computation is compatible with the OpenCL kernel execution model, and memory transfers and architecture are arranged to match the same optimization criteria as for kernel execution in GPU architectures but, differently to other approaches, with dynamic hardware execution support. In this paper, a novel design methodology for multithreaded hardware accelerators is presented. The proposed framework provides OpenCL compatibility by implementing a memory model based on shared memory between host and compute device, which removes the overhead imposed by data transferences at global memory level, and local memories inside each accelerator, i.e. compute unit, which are connected to global memory through optimized DMA links. These local memories provide unified access, i.e. a continuous memory map, from the host side, but are divided in a configurable number of independent banks (to increase available ports) from the processing elements side to fully exploit data-level parallelism. Experimental results show OpenCL model compliance using multithreaded hardware accelerators and enhanced dynamic adaptation capabilities.

In order to cope with increasing competition, high-tech firms need to continuously launch new products. However, adoption of new products may require substantive cognitive efforts from consumers. Therefore, firms should be able to monitor and influence their consumer's knowledge base. The aim of this paper is to evaluate the usability of a consumer learning roadmap for high-tech marketing. A tentative framework is built based on the previous literature on innovation adoption and consumers' knowledge development. The usability of this framework is then evaluated on the basis of case studies. The study indicates that in case innovations, firms were actively triggering, monitoring and guiding consumer's knowledge base in order to promote the adoption of successive product generations. This supports the idea that a consumer learning roadmap is a relevant and indeed a successful concept for high-tech marketing. The fact that a consumer learning roadmap has so far been used only marginally means that the most prominent high-technology marketers are likely, little by little, to dominate their market.

The OpenCL standard allows targeting a large variety of CPU, GPU and accelerator architectures using a single unified programming interface and language. But guaranteeing portability relies heavily on platform-specific implementations. In this paper, we provide an OpenCL implementation on an ARMv8 multi-core CPU, which efficiently maps the generic OpenCL platform model to the ARMv8 multi-core architecture. With this implementation, we first characterize the maximum achieved arithmetic throughput and memory accessing bandwidth on the architecture, and measure the OpenCL-related overheads. Our results demonstrate that there exists an optimization room for improving OpenCL kernel performance. Then, we compare the performance of OpenCL against serial codes and OpenMP codes with 11 benchmarks. The experimental results show that (1) the OpenCL implementation can achieve an average speedup of 6X compared to its OpenMP counterpart, and (2) the GPU-specified OpenCL codes are often unsuitable for this ARMv8 multi-core CPU.

GPU-accelerated Chemical Similarity Assessment for Large Scale Databases.

Optimal Marketing Entry Timing for Successive Product/Service Generations

The computation grows quadratically with increase in sequences that needs to be aligned. The sequence alignment needs improvement in execution speed with the increase in database size. Dynamic programming approach if applied to search databases then it can be computationally expensive so it needs hardware-based acceleration like GPU which helps in searching databases quickly. Instead of using single threaded CPU based computing if computing capability of CPU and GPU are combined together then this hybrid approach results in much faster computation than the sequential approach. This improvement utilizes the parallel architecture of GPU for high performance computing. This improved strategy outperforms single threaded CPU based computing. Both performances are compared with different lengths of sequences. This paper also compares the parallel strategy by comparing different types of available GPU, types of memory access and different types of alignment algorithms on different benchmarks.

As computation schemes evolve and many new tools become available to programmers to enhance the performance of their applications, many programmers started to look towards highly parallel platforms such as Graphical Processing Unit (GPU). Offloading computations that can take advantage of the architecture of the GPU is a technique that has proven fruitful in recent years. This technology enhances the speed and responsiveness of applications. Also, as a side effect, it reduces the power requirements for those applications and therefore extends portable devices battery life and helps computing clusters to run more power efficiently. Many performance analysis tools such as LTTng, strace and SystemTap already allow Central Processing Unit (CPU) tracing and help programmers to use CPU resources more efficiently. On the GPU side, different tools such as Nvidia’s Nsight, AMD’s CodeXL, and third party TAU and VampirTrace allow tracing Application Programming Interface (API) calls and OpenCL kernel execution. These tools are useful but are completely separate, and none of them allow a unified CPU-GPU tracing experience. We propose an extension to the existing scalable and highly efficient LTTng tracing platform to allow unified tracing of GPU along with CPU’s full tracing capabilities.