Incorporating Performance Portability and Data-Oriented Design in Phase-Field Modeling

Efficiently simulating solid mechanics is vital across various engineering applications. As constitutive models grow more complex and simulations scale up in size, harnessing the capabilities of modern computer architectures has become essential for achieving timely results. This paper presents advancements in running parallel simulations of solid mechanics on multi-core CPUs and GPUs using a single-code implementation. This portability is made possible by the C++ matrix and array (MATAR) library, which interfaces with the C++ Kokkos library, enabling the selection of fine-grained parallelism backends (e.g., CUDA, HIP, OpenMP, pthreads, etc.) at compile time. MATAR simplifies the transition from Fortran to C++ and Kokkos, making it easier to modernize legacy solid mechanics codes. We applied this approach to modernize a suite of constitutive models and to demonstrate substantial performance improvements across different computer architectures. This paper includes comparative performance studies using multi-core CPUs along with AMD and NVIDIA GPUs. Results are presented using a hypoelastic–plastic model, a crystal plasticity model, and the viscoplastic self-consistent generalized material model (VPSC-GMM). The results underscore the potential of using the MATAR library and modern computer architectures to accelerate solid mechanics simulations.

The emergence of accelerator-based computer architectures and programming models makes it challenging to achieve performance portability for large-scale scientific simulation software. In this paper, we focus on a sparse block diagonal matrix multiple vector (SpMM) computational kernel and discuss techniques that can be used to achieve performance portability on NVIDIA and AMD based accelerators using CUDA, HIP, OpenACC, Kokkos. We show that performance portability can vary significantly across programming models, GPU architectures, and problem settings, by up to 52× in the explored problems. Our study visits the performance portability aggregation techniques to guide the development and the selection of performance portable algorithmic variants.

Algorithms of dense stereovision can be of great interest for designing computer vision systems of autonomous mobile objects. In the process of computing dense stereo, on the one hand, a lot of arithmetic operations are performed and a significant memory resource is required, and, on the other hand, the majority of dense stereovision algorithms can be parallelized. Different modern computer architectures available for processing data from stereo sensors can be named. While choosing certain architecture it is necessary to take into consideration energy efficiency, performance and dimensions of final algorithm implementation. The article gives justification to choose the algorithm of dense stereovision and analyzes its efficiency on different calculators. The analysis is performed on three different architectures: classic CPU, GPU and FPGA. The aim of the analysis is to find the best architecture to suit the task of using dense stereovision algorithms in mobile systems of computer vision.

Modern computer architectures have evolved from uni-processor platforms to multi-processor and multi-core platforms, but traditional real-time distributed middleware such as RT-CORBA has not kept pace with that evolution. To address those issues, this paper describes the design and implementation of MCFlow, a new real-time distributed middleware for dependent task graphs running on multi-core platforms. MCFlow provides the following contributions to the state of the art in real-time middleware: (1) it provides an efficient C++ based component model through which computations can be configured flexibly for execution within a single core, across cores of a common host, or spanning multiple hosts; (2) it allows optimizations for inter-component communication to avoid data copying without sacrificing the parallel executability of data dependent tasks; (3) it strictly separates timing and functional concerns of an application so that they can evolve and can be configured independently; and (4) it provides a novel event dispatching architecture that uses lock free algorithms to avoid mutex locking and reduce memory contention, CPU context switching, and priority inversion. We also present an empirical evaluation that demonstrates the efficacy of our approach. Type of Report: Other Department of Computer Science & Engineering Washington University in St. Louis Campus Box 1045 St. Louis, MO 63130 ph: (314) 935-6160 The Design and Implementation of MCFlow: a Real-time Multi-core Aware Middleware for Dependent Task Graphs Huang-Ming Huang, Christopher Gill, Chengyang Lu Department of Computer Science and Engineering, Washington University St. Louis, MO, USA {hh1, cdgill, lu}@cse.wustl.edu Abstract—Modern computer architectures have evolved from uni-processor platforms to multi-processor and multi-core platforms, but traditional real-time distributed middleware such as RT-CORBA has not kept pace with that evolution. To address those issues, this paper describes the design and implementation of MCFlow, a new real-time distributed middleware for dependent task graphs running on multi-core platforms. MCFlow provides the following contributions to the state of the art in real-time middleware: (1) it provides an efficient C++ based component model through which computations can be configured flexibly for execution within a single core, across cores of a common host, or spanning multiple hosts; (2) it allows optimizations for inter-component communication to avoid data copying without sacrificing the parallel executability of data dependent tasks; (3) it strictly separates timing and functional concerns of an application so that they can evolve and can be configured independently; and (4) it provides a novel event dispatching architecture that uses lock free algorithms to avoid mutex locking and reduce memory contention, CPU context switching, and priority inversion. We also present an empirical evaluation that demonstrates the efficacy of our approach.Modern computer architectures have evolved from uni-processor platforms to multi-processor and multi-core platforms, but traditional real-time distributed middleware such as RT-CORBA has not kept pace with that evolution. To address those issues, this paper describes the design and implementation of MCFlow, a new real-time distributed middleware for dependent task graphs running on multi-core platforms. MCFlow provides the following contributions to the state of the art in real-time middleware: (1) it provides an efficient C++ based component model through which computations can be configured flexibly for execution within a single core, across cores of a common host, or spanning multiple hosts; (2) it allows optimizations for inter-component communication to avoid data copying without sacrificing the parallel executability of data dependent tasks; (3) it strictly separates timing and functional concerns of an application so that they can evolve and can be configured independently; and (4) it provides a novel event dispatching architecture that uses lock free algorithms to avoid mutex locking and reduce memory contention, CPU context switching, and priority inversion. We also present an empirical evaluation that demonstrates the efficacy of our approach. Keywords-component; middleware

In this paper we describe an algorithm visiting all numerical semigroups up to a given genus using a well-suited representation. The interest of this algorithm is that it fits particularly well the architecture of modern computers allowing very large optimizations: we obtain the number of numerical semigroups of genus g ⩽ 67 g\leqslant 67 and we confirm the Wilf conjecture for g ⩽ 60 g\leqslant 60 .

Perceived benefits of the heterogeneous computing models have led to GPUs becoming an indispensable part of existing/future HPC infrastructures. The semiconductor industry has enabled a continuous increase in computing capabilities of GPUs across successive product generations. In this light, performance portability of applications across different generations of GPUs with minimal programmer intervention, is desired. There is, however a lack of tool-chain support that can help with porting applications across GPUs with myriad computing capabilities. In this paper, we propose an Auto-Tune tool for OmpSs-OpenCL kernels to ease the process of porting applications across different generations of GPUs. The proposed tool focuses on modifying the OpenCL kernel execution configuration based on GPU specifications and does not require any user intervention providing reasonable performance portability. We evaluate our proposal on 7 different benchmarks with varied characteristics ported across three different GPU architectures. In addition, the Auto-Tune tool integrated with OmpSs-OpenCL offered a maximum performance gain of 10% for Matmul workload at runtime.

Variance estimation in multistage sampling without replacement usually requires considerable computational effort. One option is to implement explicit formulas on a computer, at least for some specific sampling designs. This approach becomes quite cumbersome to handle beyond two stages, both from the formulation and computer implementation points of view. Another option is to provide a general method to compute variance estimates for any number of stages. Such an approach may involve data structures and estimators which are recursively defined.•The solution we present in this article is intended to be both general and computationally efficient by relying on a full-iterative implementation.•The definition of the estimators remains implicit as in the recursive approach, but is expressed in terms of recurrence relations translated into iterative algorithms.•These algorithms rely only on (dense) array data structures. Moreover, most of the necessary computer memory is only used during preliminary steps and is not required when performing the statistical calculations.

Numerical solution to phase-field model of solidification: A review

This paper traces the history of computer architecture courses in electrical engineering departments. Previously unpublished data from the Fall 1972 COSINE survey are given to show current computer architecture course offerings and texts. Computer architecture courses offered in 1972-73 are analyzed, compared with ACM and COSINE recommendations, and classified into five categories: introductory computer engineering courses with a computer architecture flavor, software-oriented computer organization courses, hardware-oriented computer organization courses, case study courses, and topical seminars. Future trends in computer architecture education are predicted.

The introduction of vector and parallel supercomputers in the last decade generates a significant impact on large-scale scientific computing. Computational optimization is one important area that is rapidly evolving to benefit from novel computer architectures. In this paper, we restrict our discussions to numerical methods for nonlinear unconstrained optimization. Many important applications fall into this category, and these methods often serve as the basis for other iterative procedures that are generally used in solving nonlinear programming problems. There exists a large array of methods for solving nonlinear unconstrained optimization problems Various implementations of many of these methods can be obtained from the open literature including journals and textbooks. Only a selective number of those techniques have been shown to be most robust and efficient; some of them are currently distributed as commercial software libraries. Testing and comparing these optimization codes is very important since it provides some prior measure of efficiency and robustness of the codes and will show the suitability of a code for solving a particular application problem at hand. Although many numerical evaluations of unconstrained optimization methods have been published, most of them were geared towards relatively small dimensional problems, and very few of them were based on implementations available in public software libraries. Comparison of specific implementations is necessary since the performance of a particular algorithm can vary widely from implementation to implementation. Technical details of the programming and slight changes in the line search techniques, restart criterion, updating formulas, and the like could make a significant difference in the performance of an algorithm. In this paper, we compare the performances of several unconstrained optimization codes available in the leading numerical libraries. These software libraries receive widespread usage in the scientific community worldwide. In particular, we are interested in solving problems for which the number of variables n is of medium to large size, say up to 10,000 variables. Numerical results are obtained using an NEC SX-IA supercomputer.

The increasing urge to bypass the issue of the memory bottleneck in the current computer architectures has attracted high attention to in-memory computing enabled by emerging memory technologies such as Resistive Random Access Memory (RRAM). This paper studies in-memory computing from two perspectives, i.e. customized and instruction-based. The customized approach exploits logic representations to synthesize for in-memory computing. The approach proposes design methodologies and optimization algorithms for each representation with respect to area and latency upon the realizations of their logic primitives. The instruction-based approach proposes an automatic compiler to execute instructions on a logic-in-memory computer architecture and optimizes the programs. Experimental results for both approaches reveal considerable improvements compared to the state-of-the-art.

We present an MPI based software library for computing fast Fourier transforms (FFTs) on massively parallel, distributed memory architectures based on the Message Passing Interface standard (MPI). Similar to established transpose FFT algorithms, we propose a parallel FFT framework that is based on a combination of local FFTs, local data permutations, and global data transpositions. This framework can be generalized to arbitrary multidimensional data and process meshes. All performance-relevant building blocks can be implemented with the help of the FFTW software library. Therefore, our library offers great flexibility and portable performance. Similarly to FFTW, we are able to compute FFTs of complex data, real data, and even- or odd-symmetric real data. All the transforms can be performed completely in place. Furthermore, we propose an algorithm to calculate pruned FFTs more efficiently on distributed memory architectures. For example, we provide performance measurements of FFTs of sizes between $512^3$ ...

Accelerating LASG/IAP climate system ocean model version 3 for performance portability using Kokkos

Compiler-based code generation and autotuning for geometric multigrid on GPU-accelerated supercomputers

Human safety is one of the most critical factors when a new technology is introduced to the everyday use. It was no different in the case of Autonomous Vehicles (AV), designed to replace generally available Conventional Vehicles (CV) in the future. AV rules, from the start, focus on guaranteeing safety for passengers and other road users, and these assumptions usually work during normal traffic conditions. However, there is still a problem with proper reaction time to sudden, dangerous and unexpected scenarios like a running animal on a rural road during the night. In this paper, we compare human and AV responses to sudden scenarios and accidents. As the AV topic can be analyzed as an ICT system, we review modern sensors, computer architectures and algorithms designed for this type of problems. Beside regular analysis, we also show which algorithms can run simultaneously and if vehicles have proper tools to guarantee safety during regular system delays. As a final result, we present a diagram which depicts Autonomous Vehicle logic and allows to identify bottlenecks. Additionally, the analysis shows how different refresh rates and algorithm execution times can affect the braking distance thus safety of other road users.