Automated Design Flow for Multi-Functional Dataflow-Based Platforms

To assess the performance of forthcoming 4th generation wireless local area networks, the algorithmic functionality is usually modelled using a high-level mathematical software package, for instance, Matlab. In order to validate the modelling assumptions against the real physical world, the high-level functional model needs to be translated into a prototype. A systematic system design methodology proves very valuable, since it avoids, or, at least reduces, numerous design iterations. In this paper, we propose a novel Matlab-to-hardware design flow, which allows to map the algorithmic functionality onto the target prototyping platform in a systematic and reproducible way. The proposed design flow is partly manual and partly tool assisted. It is shown that the proposed design flow allows to use the same testbench throughout the whole design flow and avoids time-consuming and error-prone intermediate translation steps.

High-speed permanent-magnet synchronous machines (HS PMSMs) are a popular topology among modern electrical machines. Suitable applications for such machines are low-power vacuum pumps, compressors, and chillers. This paper describes a systematic design methodology for an HS PMSM using two case studies. The design process for such high-speed (HS) machines is multidisciplinary and highly iterative due to the complex interaction of the many design variables involved. Consequently, no single optimum solution exists, and multiple possible solutions can meet the customer requirements. Practical solutions should be within acceptable thermal limits, should be energy-efficient, and should be rigid enough to withstand the forces exerted during operation. The proposed design flow is divided into steps that are presented in this paper in the form of a flowchart with emphasis on mechanical aspects. Each step represents a task for a thermal, mechanical, or electrical engineer. The features of each step and the prerequisites for moving to the next step are discussed. The described methodology was implemented in the design of two HS PMSMs. The output performance results of the design flow are compared with measured results of the prototypes. The design process described in this paper provides a straightforward procedure for the multidisciplinary design of HS permanent magnet electrical machines.

A System Level Design Flow for Embedded Systems based on Model of Computation Mappings

Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems

This paper proposes an improved ASIC design flow for the automotive ASIC development. Using a FPGA based hardware prototype verification step, the improved design flow enables the test of entire design in a running automotive module with different operating conditions, helps to find out issues before the tape out. The proposed design flow can largely increase the confidence level in the tape out, decrease the development time, reduce the risk of multiple re-spin cycles, and lead to a better cost efficiency in the automotive ASIC development. A diesel engine driver circuit design example is used to explain this proposed design flow. The prototype test setting and measurement results are also presented.

This paper presents a new transistor level design flow where it is possible to optimize the circuit with a wide number of logic functions and drive strengths. Different from the standard cell approach, our methodology is not limited to a previously characterized library of cells. The proposed design flow provides a virtual library with around 15,000 cells for logic synthesis and performs a transistor sizing optimization step to improve the timing of the circuit during layout generation. A transistor-level layout generator allows to explore these wide number of cells and drive strengths while optimizing the layout concerning connections and transistors. Circuits generated by our methodology were compared to the standard cell approach in which presented around 11 % of delay improvement and more than 30% of power savings.

A system on chip (SoC) library for MOSIS scalable CMOS rules has been developed It is intended for use with Synopsys and Cadence Design Systems electronic design automation tools. Students can also use layout tools for semi-custom designs and insert them with the proposed design flow. Scalable submicron rules are used for the cell library, allowing it to be used for several AMI and TSMC technologies. Consequently, it is possible to fabricate student projects as well as do research in system on chip design through the MOSIS educational program. All steps in the design flow are fully automated with scripts and have been tested successfully in a large VLSI design class at the Illinois Institute of Technology.

The paper presents a design methodology for distributed applications of networked embedded systems. The original contribution is the joint perspective on communication aspects and dependability. The methodology allows to model the dependability requirements of the application under design and the degree of dependability of involved components, like nodes, communication protocols, and channels. By assessing the dependability degree of a candidate solution, the methodology allows to iterate the synthesis process until requirements are met. The effectiveness of the proposed design flow is shown by an actual case study.

In VLSI design flow, the designer has better control over critical parameters such as power consumption and delay at higher levels of abstraction. Trade-offs and design changes are easier to accomplish at architectural and system levels. The decisions taken at these levels have a large impact on the final quality of the design. Power consumption has become a vital issue in all modern designs. However, actual information on this important metric is available only after the back-end phase when the design is committed to silicon. At this juncture, very little can be done to optimize power. Therefore, power estimation at higher levels is an extremely crucial step in executing power aware designs. Power estimation techniques can be applied at all abstraction levels in the low power design flow, of which highest level is system level. The design process at higher abstraction level shields the designer's crucial time and effort in power estimation. It is challenging to extract and analyse knowledge about the circuit of the system at the system level. If we estimate the power at this level, large power savings can be done and also power optimized design changes can be done. This paper describes an augmented power estimation methodology for intellectual property (IP) components. The method uses statistical methods to isolate a set of input influencing the output power for a particular mode of operation. The power model is developed as a function of parameters such as signal probability, transition density and spatial correlation. The proposed method was evaluated on a SDRAM controller core. The power estimation error varies from 0.3% to 12.5%.

Digital integrated circuits or intellectual property (IP) cores are widely used as computation engines or processors (application-specific and/or hardware accelerators) in sophisticated electronics products such as smartphones, cameras, camcorders, set-top boxes, smart watches, etc. Recently there has been a paradigm shift from the conventional IC/IP design flow to a secured IC/IP design flow that considers security awareness during the design process. Security awareness during the design process includes considering preventive/detective control measures while synthesizing an IC/IP. Security aware design flow is specifically important in this modern era of global design supply chain where trustworthiness of IC/IP has become a serious problem giving rise to hardware threats such as piracy, backdoor Trojan insertion, etc. This chapter will provide a discussion on some of the latest hardware security and IC/IP core protection methodologies integrated within the high-level synthesis design flow, such as structural obfuscation, functional obfuscation and hardware watermarking, including some case study analyses on DSP applications.

With continuing progress in VLSI and ASIC technologies, digital signal processing (DSP) algorithms have continued to find great use in increasingly wide application areas. DSP has gained popularity also in embedded systems although these systems set challenging constraints for implementations. Embedded systems contain limited resources, thus embedded DSP systems must balance tradeoffs between the requirements on computational power and computational resources. Energy efficiency has been important in batterypowered devices, but nowadays also the limited heat dissipation in small devices calls for low-power consumption. Successful implementation of DSP applications in embedded systems requires tailoring, which in turn sets challenges for design methodologies. For this special issue, we received 14 submissions and a collection of seven papers was finally accepted. The special issue is opened by “Observations on power-efficiency trends in mobile communication devices,” where the authors O. Silven and K. Jyrkka analyze the power consumption in the current mobile communication devices. Several bottlenecks in the current implementation style have been identified, thus the paper provides a good motivation for the following papers. In “The Sandbridge SB3011 platform,” the authors John Glossner et al. describe a system-on-a-chip (SoC) multiprocessor targeted as a software-defined radio platform. The platform provides solutions to the challenges in future mobile devices given in the previous paper. “A shared memory module for asynchronous arrays of processors” authored byMichael J. Meeuwsen et al. considers also chip multiprocessors. The presented shared memory module can be used for interprocess communication or to increase application performance by parallelizing computation. In “Implementing a WLAN video terminal using UML and fully automated design flow” by Petri Kukkala et al., an automated design flow for multiprocessor SoC is presented. The flow is based on UML descriptions and the authors demonstrate their design flow with a design case. Programming of chip multiprocessor platforms is considered in “pn: a tool for improved derivation of process networks” by Sven Verdoolaege et al. The paper discusses conversion of sequential programs to process networks allowing optimization of communication channels and buffers. In “A SystemC-based design methodology for digital signal processing systems,” the authors Christian Haubelt et al. describe a design flow for SoC designs containing automatic design space exploration, performance evaluation, and automatic platform-based system generation. The design flow is based on SystemC descriptions and the presented tools can automatically detect the underlying model of computation. Application-specific implementations are often used to speedup certain DSP tasks in embedded systems. In “Priority-based heading one detector in H.264/AVC decoding,” the authors Ke Xu et al. consider such implementations to speed up video decoding applications. The authors present a low-power decoder implementation for context-adaptive variable length coding defined in H.264 standard.

To cool a high-pressure gas turbine blade, many rows of cooling holes with different arrangements and configurations are manufactured to achieve higher cooling effect and lower aerodynamic loss. To evaluate the heat transfer and film cooling effect in the full-cooled turbine blade, efficient numerical simulations are required in the design and performance optimization processes. From the view of numerical accuracy, the structured grids have to be employed because of higher resolution in flow and heat transfer than the unstructured grids. Because many splitting, attaching and merging manipulations are involved in meshing the cooling features and curved boundaries, it is very complex and time-consuming for a researcher to generate multi-block structured grids for a full-cooled gas turbine blade. As a result, in the industrial applications, almost all researchers preferred to generate unstructured grids instead of structured grids for the full-cooled blade. Unlike the previous research, the aim of this study is to apply the Background-Grid Based Mapping (BGBM) method proposed in Part I to generate multi-block structured grids for a full-cooled gas turbine vane. With the strategy of BGBM method, meshes were conveniently generated in the computational space with simple geometrical features and plain interfaces, and then were mapped back into physical space to obtain the multi-block structured grids which can be used for numerical simulations. With the experimental data, the present numerical methods and BGBM strategy were carefully validated. Then, the flow and film cooling performance in the full-cooled NASA GE-E3 nozzle guided vane were numerically investigated. The effects of coolant mass flow rate and land extensions on film cooling effectiveness were discussed. The results show that film cooling effectiveness near the stagnation point is the lowest and film cooling effectiveness on the pressure side is slightly higher than that on the suction side. When the coolant mass flow rate increases up to the value of 1.5 design flow, the relative outflow mass flow rates of cooling hole arrays and slots are no longer affected by the increase of the coolant flow rate. At half design flow, the outflow mass flow rates of No.5 hole-array to No.10 hole-array are almost zero, and the area-averaged film cooling effectiveness on vane surface is as low as 0.268. Compared with the cases of half design flow and double design flow, better film cooling performance is obtained in the cases of design flow and 1.5 design flow. Compared with the vane without lands, the area-average cooling effectiveness on vane surface is slightly higher for the vane with lands. Land extensions have a considerable influence on film cooling performance in the cutback region.

The purpose of “system optimization” cannot be just to improve the performance of a given, pre-configured system (search for efficiency) but rather to find the best system configuration, itself, i.e., design an optimal system (search for effectiveness). System boundaries, especially in socio-economic and engineering systems, are not conveniently given and fixed a priori, but are themselves to be determined in an optimal way. We present theory and methodology of optimal system design (or configuration), as it is embodied in de novo programming. The message is clear and simple: optimizing “badly” configured system is ineffective and wasteful while optimally designed systems hardly need any further “optimization”.

Summary form only given. For many VLSI designs, validation has started to dominate the total design effort. In addition, historical trends are indicating that this problem will continue to grow. For example, data from Intel's lead microprocessor design efforts shows that the number of pre-silicon bugs has increased by a factor of four for every lead project for the last 25 years. If this trend is not broken, Intel's next lead design is likely to have to go through the find the bug, evaluate it, root cause it, it, and validate the fix process tens of thousands of times; potentially overwhelming the validation and design team. Thus one of the most critical goals for improving the design process is to break this bug trend. In the presentation, we introduce the integrated design and verification (IDV) system that has been developed at Intel for the last 5 years. IDV combines the design and validation efforts so that the task of design validation (i.e., Did we capture what we actually wanted?) is significantly simplified by means of a much smaller and much more stable high-level model. Furthermore, when the design is completed, so also is the implementation validation (i.e., Did we implement what we intended?). The latter is accomplished by linking the design process very tightly with the validation process. Although this idea is not new, the combination of correct-by-construction and correct-by-verification and the tight integration of a database of verified results is new and has led to a design environment that allows rapid design in which the validation problem has been significantly reduced. To make the presentation more realistic, we will use the design, from a high-level model to layout, of a floating point execution unit as a driving example. We discuss the early design phase in which the high-level model is refined using algorithmic transformations to a viable micro architecture; continue with the middle level design in which the actual logic implementation is derived and conclude with the final placement and layout stage. Although the design process conceptually is performed sequentially, we will illustrate the tight loop that IDV enables between physical design and logical/micro-architectural design. The latter is a critical component in enabling design convergence. In fact, in today's process technology, integration of physical and logical design is not optional but rather mandatory.

The design of embedded systems is a complex iterative process. To shorten the design cycles, it is useful to utilize suitable intellectual properties (IPs). At some point during the service life of a product, the owner of the product might wish for additional functions in the device, even if the device is still fully functional. This can be realized by the technique of reconfiguration, a capability usually supported by prototyping platforms such as FPGAs. Automation of various portions of the embedded system design process is necessary in order to make effective use of IPs and reconfiguration capabilities. This implies the specification of a new design flow. In this paper we propose such a design flow and describe the mechanisms we developed for automation. We present relevant aspects for composing an optimized system based on IPs and detail the automatic generation of the system implementation on a prototyping platform. Finally, we give an example, which illustrates the applicability of the proposed design flow.