Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems

Network teaching is to use computer equipment and Internet technology in the virtual space, through a certain method to implement the teaching method on the network, the perfection of the network teaching system can directly replace the traditional teaching method in the whole process of teaching. In order to solve the problem of system development, this paper carries out the demand analysis. First, the use of data flow graph technology, depicting information flow and data from the input to the output of the process of transformation; and then, the use of data dictionary technology, defining the relevant elements of the data flow diagram; finally, the use of tree structure diagram is represented by the administrator subsystem, teacher subsystem and student subsystem structure of the system. The requirement analysis system design the bridge of analysis and software, has laid a foundation for the system development.

The ULowell Data Flow Project combines dataflow hardware, dataflow software, and a data flow development environment. The hardware component, a data flow coprocessor card, utilizes seven NEC 7281 Image Pipelined Processors. Each chip models a static dataflow computation and is programmable. The coprocessor was designed and implemented by ULowell personnel and uses an AMIGA 2000 as a host. The software component currently consists of a library of data flow image processing algorithms and an evolving software development environment. Currently the image processing library includes typical imaging operations such as: edge enhancement, filtering, histogramming, and affine transformation. The software development environment (SDE) is depicted in Figure 1. The SDE contains a Data Flow Graph Editor which programmers use to design their data flow code. The data flow algorithm can then be converted directly into NEC data flow assembly code which is then assembled using the ULowell Data Flow Assembler. The assembler differs from NEC's assembler in that it can produce relocatable code. The object code output of the assembler is given to the Data Flow Resource Manager. The resource manager monitors the available resources within the chips. Thus, if a single process does not totally utilize a chip's table space or memory, then a second process may be concurrently loaded onto the same chip. The ability to have multiple data flow processes coexisting within a single chip is unique to the ULowell environment. The data flow resource manager can download and monitor code to either the hardware or to a software simulator/debugger. The simulator/debugger can monitor and trace data flow tokens as they proceed through the chip. Output of the simulator/debugger can be fed back into the data flow graph editior to visually trace token flow through the original program design. The last component of our SDE is a High Level Language translator which can compile programs written in SISAL, a high level language for parallel computation, down to NEC 7281 assembly language. We have already implemented the relocatable assembler, and the data flow resource manager. Prototype versions of the high level translator, simulator/debugger and graph/editor are currently being implemented.

To assess the performance of forthcoming 4th generation wireless local area networks, the algorithmic functionality is usually modelled using a high-level mathematical software package, for instance, Matlab. In order to validate the modelling assumptions against the real physical world, the high-level functional model needs to be translated into a prototype. A systematic system design methodology proves very valuable, since it avoids, or, at least reduces, numerous design iterations. In this paper, we propose a novel Matlab-to-hardware design flow, which allows to map the algorithmic functionality onto the target prototyping platform in a systematic and reproducible way. The proposed design flow is partly manual and partly tool assisted. It is shown that the proposed design flow allows to use the same testbench throughout the whole design flow and avoids time-consuming and error-prone intermediate translation steps.

Recently, high-end reconfigurable computing systems have been built that employ Field Programmable Gate Arrays (FPGAs) as hardware accelerators for general-purpose processors. These systems not only provide new opportunities for high-performance computing, but also pose new challenges to application developers. In this paper, we build a design model for hybrid designs that utilize both the processors and the FPGAs. The model characterizes a reconfigurable computing system using various parameters. Based on the model, we propose a design methodology for hardware/software co-design. The methodology partitions workload between the processors and the FPGAs, maintains load balance in the system, and realizes scalability over multiple nodes. Designs are proposed for several computationally intensive applications: matrix multiplication, matrix factorization and the Floyd-Warshall algorithm for the all-pairs shortest-paths problem. To illustrate our ideas, the proposed hybrid designs are implemented on a Cray XD1. Experimental results show that our designs utilize both the processors and the FPGAs efficiently, and overlap most of the data transfer overheads and network communication costs with the computations. Our designs achieve up to 90% of the total performance of the nodes, and 90% of the performance predicted by the design model. In addition, our designs scale over a large number of nodes.

A System Level Design Flow for Embedded Systems based on Model of Computation Mappings

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application complexities increase year after year. As a consequence, the design process is both time and resource demanding. System configuration along with resources management and mapping remain one of the most challenging problem, particularly when runtime adaptation is required. In this direction, the ISO/IEC SC29WG11 committee (MPEG) has developed the so called MPEG-RVC standards ISO/IEC 23001-4 and 23002-4. This standard provides specifications of video codecs in the form of dataflow programs. In this paper, an integrated design flow to derive optimized multi-functional platforms directly from disjoined high-level specifications is presented. To the authors' best of knowledge, such an optimization, synthesis and mapping methodology for coarse-grained reconfigurable systems design does not exist within the MPEG-RVC framework. The design flow presented in this paper leverages on an integrated set of independently designed tools, all supporting the RVC standard. Results assessment has been carried out on three different scenarios: an MPEG-RVC decoder, a standard baseline MPEG-RVC JPEG codec and a generalized reconfigurable multi-quality JPEG encoder. For all these scenarios, the proposed design flow has been targeted for a Xilinx Virtex 5 FPGA. Results show how this approach is capable of yielding a reconfigurable design that preserves the original performance of the stand alone non-reconfigurable platform providing, at the same time, considerable area savings featuring a larger set of functionalities. Moreover, platforms programmability, on the basis of the required functionality ID, is automatically handled at runtime without any designer effort.

This paper presents a cost-effective scheme for partitioning large data flow graphs. Standard data flow machine architectures are assumed in this work. The objective is to reduce the overhead due to token transfers through the communication network of the machine. When this scheme is employed on large graphs, the load distribution on the rings of the data flow machine is also improved. A canonical form of a data flow graph is introduced to establish the relationship between the communication overhead and the size reduction of the partition cut-set. General lower estimates on the overhead are derived in terms of processing and transmission delay parameters of the machine. The method uses heuristics and an evaluation function to guide the partition algorithm. Some implications of the proposed method on the organization of the data flow machines are discussed.

A system called net optimization and resource allocation (NORA) is introduced for the evaluation and programming of parallel signal processors, based on a data flow representation of the signal processing application. The main feature of this approach is that the scheduling and resource allocation can be done at compile time. It is made possible by the fact that most signal processing algorithms have constant data flow. The resulting hardware is much simpler because no overhead is needed for the real-time scheduling, as in usual data flow systems. Therefore a realization can easily be obtained using either commercially available components or VLSI technology. The proposed system comprises four main components: (1) a vector oriented data flow compiler for the translation of a high-level language description of algorithms into a data flow graph; (2) a critical path analysis for the evaluation of the minimal computation time of the algorithm, where block scheduling is assumed; (3) a schedule optimization for the determination of the minimal computation time under limited resources, not taking into account limitations imposed by the interconnection structure and temporary storage; and (4) a combined schedule optimization and resource allocation that maps a signal processing application onto a given hardware configuration and generates a formal microprogram.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper proposes an improved ASIC design flow for the automotive ASIC development. Using a FPGA based hardware prototype verification step, the improved design flow enables the test of entire design in a running automotive module with different operating conditions, helps to find out issues before the tape out. The proposed design flow can largely increase the confidence level in the tape out, decrease the development time, reduce the risk of multiple re-spin cycles, and lead to a better cost efficiency in the automotive ASIC development. A diesel engine driver circuit design example is used to explain this proposed design flow. The prototype test setting and measurement results are also presented.

Applications in the signal processing domain are often modeled by data flow graphs which contain both dynamic and static data flow actors due to heterogeneous complexity requirements. Thus, the adopted notation to model the actors must be expressive enough to accommodate dynamic data flow actors. On the other hand, treating static data flow actors like dynamic ones hinders design tools in applying domain-specific optimization methods to static parts of the model, e.g., static scheduling. In this paper, we present a general notation and a methodology to classify an actor expressed by means of this notation into the synchronous and cyclo-static dataflow models of computation. This enables the use of a unified descriptive language to express the behavior of actors while still retaining the advantage to apply domain-specific optimization methods to parts of the system. In experiments we could improve both latency and throughput of a general data flow graph application using our proposed automatic classification in combination with a static single-processor scheduling approach by 57%.

High-speed permanent-magnet synchronous machines (HS PMSMs) are a popular topology among modern electrical machines. Suitable applications for such machines are low-power vacuum pumps, compressors, and chillers. This paper describes a systematic design methodology for an HS PMSM using two case studies. The design process for such high-speed (HS) machines is multidisciplinary and highly iterative due to the complex interaction of the many design variables involved. Consequently, no single optimum solution exists, and multiple possible solutions can meet the customer requirements. Practical solutions should be within acceptable thermal limits, should be energy-efficient, and should be rigid enough to withstand the forces exerted during operation. The proposed design flow is divided into steps that are presented in this paper in the form of a flowchart with emphasis on mechanical aspects. Each step represents a task for a thermal, mechanical, or electrical engineer. The features of each step and the prerequisites for moving to the next step are discussed. The described methodology was implemented in the design of two HS PMSMs. The output performance results of the design flow are compared with measured results of the prototypes. The design process described in this paper provides a straightforward procedure for the multidisciplinary design of HS permanent magnet electrical machines.

This paper presents a new transistor level design flow where it is possible to optimize the circuit with a wide number of logic functions and drive strengths. Different from the standard cell approach, our methodology is not limited to a previously characterized library of cells. The proposed design flow provides a virtual library with around 15,000 cells for logic synthesis and performs a transistor sizing optimization step to improve the timing of the circuit during layout generation. A transistor-level layout generator allows to explore these wide number of cells and drive strengths while optimizing the layout concerning connections and transistors. Circuits generated by our methodology were compared to the standard cell approach in which presented around 11 % of delay improvement and more than 30% of power savings.

A system on chip (SoC) library for MOSIS scalable CMOS rules has been developed It is intended for use with Synopsys and Cadence Design Systems electronic design automation tools. Students can also use layout tools for semi-custom designs and insert them with the proposed design flow. Scalable submicron rules are used for the cell library, allowing it to be used for several AMI and TSMC technologies. Consequently, it is possible to fabricate student projects as well as do research in system on chip design through the MOSIS educational program. All steps in the design flow are fully automated with scripts and have been tested successfully in a large VLSI design class at the Illinois Institute of Technology.

The paper presents a design methodology for distributed applications of networked embedded systems. The original contribution is the joint perspective on communication aspects and dependability. The methodology allows to model the dependability requirements of the application under design and the degree of dependability of involved components, like nodes, communication protocols, and channels. By assessing the dependability degree of a candidate solution, the methodology allows to iterate the synthesis process until requirements are met. The effectiveness of the proposed design flow is shown by an actual case study.

In the pursuit of massively multiplayer online games, efficient engines capable of processing sophisticated game scenarios are necessary to support large scale virtual worlds. By applying microprocessor microarchitectural design techniques to game server software design, functional parallelism inherent in complex game transactions can be exploited, augmenting server performance.In a given gaming scenario, complex game transactions can be modeled as data flow graphs. An individual graph represents the collective atomic operations of a particular transaction. Analysis of data flow graphs provides a mechanism that identifies opportunities for parallelism by exposing data dependencies.This poster presents an engine architecture that supports spatial and temporal parallel execution of complex game transactions expressed as data flow graphs. The engine takes advantage of data flow enhancement techniques such as dynamic out-of-order execution to achieve a high level of performance.