Automatic detection method for BGA defects based on x-ray imaging.

The current plastic Ball Grid Array (BGA) package has some disadvantages such as low level of solder crack resistance, large package warpage, and low cost performance at molding. In this paper, the author examined the improvement of the solder crack resistance, warpage and cost performance for a BGA. Firstly, solder crack resistance: as the author examined various combinations of materials used for the BGA package (molding compounds, die attach paste, and substates), it became clear that the molding compound is the most important factor for improvement of solder crack resistance. Also the molding compound factors which are necessary to withstand JEDEC level 2 treatment can be conjectured as the result of analysis of water absorption of the BGA package. Secondly, warpage: the author estimated warpage of a BGA when low Tg (below 175/spl deg/C) molding compound is used. In case of high Tg (about 180 to 200/spl deg/C) molding compound warpage can be calculated by an ideal elastic model. However, in case of low Tg it was clear that the visco-elasticity model of a polymer network is important for calculation. Thirdly, the cost performance of molding: a molding compound that can satisfy all of a plasma processing-less, short-cycle time (cure time 60 seconds), and post-cure-less for the improvement of cost performance, was examined. However, it seems difficult to satisfy all of the above items with a compound due to the problem of decrease of adhesion strength between the molding compound and the solder resist, at present.

The trend towards ultra-miniaturization, high interconnection densities with minimal power consumption at low cost is driving the need for large, thin, high-stiffness substrate technologies. Glass substrates have emerged as a promising alternative to organic and silicon interposer packages due to their tunable coefficient of thermal expansion (CTE), high dimensional stability and surface smoothness, outstanding electrical properties and low-cost panel-level processability. This paper presents a comprehensive study of the effect of glass CTE on board-level reliability of 100µm-thick glass ball grid array (BGA) packages, 18.5 mm x 18.5 mm in body size, with considerations of yield, warpage and thermal cycling performance. Polymer collars and novel doped solder alloys were also introduced to further enhance board-level reliability, and subsequently demonstrate the extendibility of direct SMT assembly of glass BGA packages to even larger body sizes. The test vehicle used in this study was an emulator of a single-chip application processor package. Daisy chain test dies, 10mm x 10mm in size and 100-200µm in thickness, were assembled onto the fabricated glass substrates with Si-matching CTE (3.8ppm/K) and board-matching CTE (9.8ppm/K) by dip-flux thermo-compression bonding with capillary underfill, at panel level. A stencil-based paste printing process was developed and optimized for panel-level balling of the glass packages with 250µm BGA at 400µm pitch. Variations in solder alloys were considered, including standard SAC105 and SAC305 used as reference, and the novel Mn-doped SACm by Indium Corporation. After singulation by laser dicing, the glass packages were finally mounted on mother boards by standard SMT reflow, after optimization of the heating profile to minimize solder voiding. Board-level yield was evaluated to 91%, and explained based on Shadow-Moire warpage measurements, showing a strong dependence to the chip-level underfill fillet size. Initial thermal cycling reliability was conducted on the glass BGA packages with and without polymer collars. All samples passed 600 cycles with stable daisy chain resistances, regardless of the glass CTE and solder alloy composition.

Power integrity (PI) is among the main concerns in the design process of multilayer packages and printed circuit boards (PCBs). Based on Transmission Matrix Method (TMM), the PI performance of a Ball grid array (BGA) package mounted on a PCB is investigated in this paper. The power/ground planes and the power/ground balls on a PCB and package are entirely equivalent to distributed RLGC circuits model and co-analyzed. From this model, power performance could be computed with high efficiency. Moreover, a design rule of power/ground balls arrangement is obtained by reducing the equivalent inductance and equivalent capacitance of BGA for good power integrity performance.

This work researched the opportunity of application of aluminum thermomigration technology for fabrication of silicon packages. The thermomigration process is also called temperature gradient zone melting. The process was used for production of through-wafer interconnections. We describe both the process and the apparatus designed for making recrystallized doped regions during heating of a silicon wafer under a temperature gradient created along the wafer thickness. In addition, we also consider three types packages which would be possible to be made by aluminum thermomigration technology: ordinary silicon ball grid array (BGA) package, combined silicon BGA package and silicon-and-silicon BGA package.

To provide electronics packages with sufficient cooling during applications to secure improved reliability and performance of the packages has been one of the challenging tasks for their manufacturers and end users. Since the introduction of the standard ball grid array (BGA) package, continued efforts by package developers have successively resulted in a family of thermally enhanced BGA packages. The extra performance BGA (XP-BGA) package is one of its latest members developed as a cost competitive package for thermal margin. To demonstrate the effectiveness of the XP concept introduced by UTAC, this paper assessed the thermal performance for the two typical BGA families, i.e. FBGA 15times15mm and PBGA 35times35mm, by applying different thermal enhancement methods. Simulation shows that thermal resistance can be reduced by 17% and 25% for XP-FBGA 15times15mm and XP-PBGA 35times35mm respectively at still air comparing with their standard BGA versions. Package thermal performance was observed to improve even more at moving air. Three-dimensional finite volume simulations were further utilized to analyze the impact of several XP related variables on the package thermal performance. XP-FBGA 15times15mm and XP-PBGA 40times40mm multi-chip package (MCP) were selected as test vehicles to study their thermal performance sensitivity to the change of design, materials, process and application environment. The development of XP-BGA achieving thermal performance comparable to that of an EBGA is realized with much lower cost and higher throughput. Package structures, CFD models, and simulation data are presented and discussed

Accelerated temperature cycling (ATC) was used to assess the thermal fatigue reliability of a Pb free, 37.5 mm fully populated, 1295 I/O ball grid array (BGA) package assembled with backward compatible or mixed alloy (Pb free BGA/SnPb paste) processing. The Pb-free BGA components were fabricated with Sn-4.0Ag-0.5Cu (SAC 405) solder balls. The surface mount assembly was done using several custom SnPb eutectic soldering profiles designed to produce different levels of Pb mixing in the BGA solder balls. The test program also included SAC405-SAC405 assemblies for reliability comparisons. The temperature cycling and metallographic data indicate that assembly parameters that produce the lowest level of Pb mixing degrade the solder joint fatigue reliability. Failure analysis demonstrates that the lower reliability is due to poorly formed solder joints resulting from incomplete reflow. The failed solder joints exhibit inadequate BGA ball collapse, minimal Pb mixing, and fatigue failure at the printed circuit board (PCB) side of the joints instead of the package-side fatigue failures that are typical for ATC testing. The test cells with more complete Pb mixing and the pure Pb-free test cell exhibited better fatigue reliability. However, failure analysis of these samples revealed that the data were compromised by the occurrence of a second failure mode in plated through hole vias that were incorporated into the PCB test vehicle. The presence of mixed mode failures (solder joint and via) precluded direct quantitative comparisons among all the test cells. The results are discussed within the context of previously published test results from the literature, including the impact of the contribution of via failures. Recommendations are outlined for additional testing to quantify the relationships between Pb mixing level and Pb-free reliability for this high density BGA package.

The delivery time of a semiconductor packaging product has developed in a very short time period due to the demanding of 3C electronics. It is a fact that liability test of an electronic package takes much time and cost, and is a key issue in delivery time for advanced electronic packages. Recently, BGA packages using SnPb alloy are popular because of its advantage of mechanical stability and good solder ability. However, lead related materials can cause hazer to human health and environmental pollution thus Union has started to implement regulations such as WEEE and RoHS to limit the amount of electrical and electronic waste materials contain toxic substances and restrict the use of lead related materials. Today lead-free solder using Sn/Ag/Cu has been developed and implanted in ball grid array (BGA) packages, and specific liability tests for this new materials are required before delivery to the market. Since thermal cycling test (TCT) is a necessary testing with time consuming that can cause delay of the products to the market. We present the evaluation of the shear strength of the solder ball with various testing parameters such as temperature different, dwell time, and cycle times in TCT, and to formulate the.

A nonlinear finite element analysis was carried out to investigate the viscoplastic deformation of solder joints in a ball grid array (BGA) package under temperature cycling. The effects of constraint on print circuit board (PCB) and stiffness of substrate on the deformation behaviour of the solder joints were also studied The results indicated that high inelastic strain was developed in the joints close to the package center. On the other hand, high constraint was associated with the joint closest to the edge of the silicon chip. Increasing external constraint on the PCB caused a slight increase in stress triaxiality in the joint closest to the edge of silicon chip. There was an increase of inelastic strain in the solder joints with increasing the Young's modulus of the substrate.

The electronics industry is switching the majority of their mobile roadmaps to Ball Grid Array (BGA) packages in order to enable thinner form factor devices. Original Equipment Manufacturers (OEMs) have to solder down the packages to their production boards since there is no form-factor production BGA socket available in the industry. This raises several challenges for the OEM supply chain and increases overall product costs. In addition to the overall added height of the socket, one technical challenge that faces the OEM BGA socket is the long-term reliability of the interface between the socket's gold-plated contacts and the package's SAC solder balls. This non-noble metal interface creates the risk of intermetallic formation and growth over the product life cycle, which will cause a bond formation and affect the removability of the BGA; it could also increase the overall resistance of the next socketing cycle due to the intermetallic residue left on the pins. This paper presents an attempt to overcome the interface challenge by re-balling the BGA with gold-plated copper spheres. Several design and SMT process parameters affect the overall re-balling quality. In particular, solder wicking is a major challenge. This paper presents an attempt to optimize the design and SMT process parameters for better results. Pad size, pad define, stencil thickness, stencil aperture size, copper sphere size, and reflow oven vs. SRT are some of the parameters that were studied.

Flip-chip carriers have become the preferred solution for high-performance ASIC and microprocessor devices. Typically these are packaged in organic or ceramic Ball Grid Array (BGA) packages. IBM has developed both Ceramic Ball Grid Array (CBGA) and Ceramic Column Grid Array (CCGA) packages which cover a wide range of package I/O capabilities required for high-performance devices, typically between 300 to more than 1600 I/O. Recently, there has been a lot of interest in Pb-free solders to replace typical Pb-based solders such as eutectic Sn-Pb used for balls in plastic BGAs (PBGA) for their assembly. The common feature of all proposed Pb-free solder alloys to date is that they are all Sn-based solders with the wt.% of Sn in the alloy typically greater than 90%. Antimony-based lead-free solders have been considered, but recently there has been a concern over the use of antimony (Sb) as well. The leading antimony-free (Sb-free) solder that has emerged from various Pb-free solder evaluations by industry and academic consortia at present is: 95.5Sn/3.8Ag/0.7Cu (SAC). The primary issues with changing from high-Pb based solders that are used in BGA assembly to electronic cards are: (1) wettability of the Pb-free solders to both Ni/Au I/O pads typically used in ceramic BGAs and card lands (Cu or Cu tinned with solder paste) with water soluble or no-clean fluxes; (2) the rate of intermetallic growth and its structure, with much higher Sn containing Pb-free solders; and (3) thermal fatigue reliability of the CBGA joints to organic cards. In this paper, initial assessment of a few leading Pb-free solders regarding wettability, microstructure and thermal fatigue life for CBGA applications is presented.

Ball grid array (BGA) packages are a relatively package type and have rapidly become the package style of choice. Much high density, high I/O count semiconductor devices are now only offered in this package style. Designers are naturally concerned about the robustness of BGA packages in a vibration environment when their experience base is with products using more traditional compliant gull or J leaded surface mount packages. Because designers simply do not have the experience, tools are needed to assess the vibration fatigue life of BGA packages during early design stages and not have to wait for product qualification testing, or field returns, to determine if a problem exists. This paper emphasizes a rapid assessment methodology to determine fatigue life of BGA components. If time and money were not an issue, clearly one would use a general-purpose finite element program to determine the dynamic response of the printed circuit board (PCB) in the vibration environment. Once the response of the PCB was determined, one would determine the location and value of the critical stress in the component of interest. Knowing the critical stress, one would estimate the fatigue life from a damage model. The time required building the finite element analysis (FEA) model, conducting the analysis, and postprocess the results would take at least a few days to weeks. This is too time-consuming, except in the most critical applications. It is not a process that can be used in everyday design and what-if simulations. The rapid assessment approach proposed in this paper focuses on a physics of failure type approach to damage analysis and involves global and local modeling to determine the critical stress in the component of interest. A fatigue damage model then estimates the life. The entire fatigue life assessment is anticipated to be executed by an average engineer in real time and take only minutes to generate accurate results.

A thermo-mechanical loading system, which can superimpose a temperature and location dependent strain on solder joints, is proposed in order to conduct highly accelerated thermal-mechanical cycling (HATC) tests to assess thermal fatigue reliability of Ball Grid Array (BGA) solder joints in microelectronics packages. The application of this temperature and position dependent strain produces generally similar loading modes (shear and tension) encountered by BGA solder joints during service, but substantially enhances the inelastic strain accumulated during thermal cycling over the same temperature range as conventional ATC (accelerated thermal cycling) tests, thereby leading to a substantial acceleration of low-cycle fatigue damage. Finite element analysis was conducted to aid the design of experimental apparatus and to predict the fatigue life of solder joints in HATC testing. Detailed analysis of the loading locations required to produce failure at the appropriate joint (next to the die-edge ball) under the appropriate tension/shear stress partition are presented. The simulations showed that the proposed HATC test constitutes a valid methodology for further accelerating conventional ATC tests. An experimental apparatus, capable of applying the requisite loads to a BGA package was constructed, and experiments were conducted under both HATC and ATC conditions. It is shown that HATC proffers much reduced cycling times compared to ATC.

In the surface mount technology, Ball Grid Array (BGA) has been used in a production of PC boards, because of their excellent characters such as high density of the lead pin pitch, better lead rigidity and self-alignment during re-flow processing. This paper deals with the development of image analysis for the detection of defects at BGA solder joints in PC boards by using X-ray images. In the conventional IC boards, it is possible to detect defects of solder joints by visual inspection, because the lead of IC package is set on its outside. However, we can't detect visually defects at BGA solder joints, because they are hidden under the IC package. In a production line, the inspection of BGA in PC boards depends on the function test of electric circuits in the final process. To improve a cost performance and the reliability of PC boards, an inspection of BGA is required in the surface mount process. Types of defects at BGA solder joints are solder bridge, missing connection, solder voids, open connection and miss-registration of parts. As we can find mostly solder bridge in these defects, we pick up this to detect solder bridge in a production line. The problems of image analysis for the detection of defects at BGA solder joints are the detection accuracy and image processing time according to a line speed of production. To get design data for the development of the inspection system, which can be used easily in the surface mount process, it is important to develop image analysis techniques based on X-ray image data. At the first step of our study, we attempt to detect the characteristic of the solder bridges based on an image analysis.

An efficient design method for flip chip ball grid array (BGA) packages has been developed. This method uses design of experiment (DOE), a series of finite element (FE) stress analyses based on an orthogonal array used in DOE, and statistical analysis. By using this method to design a BGA package having 1600 pins, the warpage of the optimum packaging structure is very small and all of the reliability demands are satisfied.

Numerical simulation and fatigue life estimation of BGA packages under random vibration loading