Automatic layout generation for digital BiCMOS cells

Increased left ventricular filling pressure is a hallmark of heart failure (HF) caused by left ventricular dysfunction (LVD). Within the closed hemodynamic system, increased LV filling pressure results in elevated pressures in the left atrium and pulmonary venous vasculature. When pulmonary hypertension (PH, defined by mean pulmonary artery pressure [mPAP] >25 mm Hg) is associated with an abnormally elevated pulmonary capillary wedge pressure (PCWP >15 mm Hg) or left ventricular end-diastolic pressure (LVEDP >18 mm Hg),1 it has been variably termed World Health Organization (WHO) Group 2 PH,1 pulmonary venous hypertension,2 “postcapillary PH,”3 or “passive PH.”4 Article see p 644 Patients with LVD also have a propensity to develop a precapillary pulmonary arterial contribution to PH, reflected by an increased transpulmonary gradient (TPG, defined as mPAP-PCWP that exceeds 12 to 15 mm Hg) or an elevated pulmonary vascular resistance (PVR, defined as TPG/cardiac output that exceeds 2.5 to 3 Wood units [WU]).5,6 This type of PH, which is “out of proportion” to underlying left-sided disease in the setting of normalized volume status, has been termed “mixed PH,” given both precapillary and postcapillary contributions to elevated PAP.7 PH in HF can be simplistically organized along 2 sequential dyads: (1) the presence or absence of a significant precapillary contribution to elevated PAP (ie, mixed PH as opposed to purely passive PH) and (2) if present, the relative fixed (ie, nonreversible with lowering left-sided filling pressures) or reactive (ie, reversible with reduction of left-sided filling pressures) character of the precapillary contribution to PH (Figure). Figure. Diagnostic framework for pulmonary hypertension in heart failure (HF). mPAP indicates mean pulmonary artery pressure; PCWP, pulmonary capillary wedge pressure; PVR, pulmonary vascular resistance; and PH, pulmonary hypertension. There are no widely established cut-points to define PVR and transpulmonary …

Preface. List of Abbreviations. 1: Introduction. 1.1. Outline of the Book. 2: Mapping Problems in the Design Flow. 2.1. Top-Down Flow and Bottom-Up Approach. 2.2. The Mapping Problem. 2.3. Placement and Routing Constraints. 3: Optimization Methods. 3.1. VLSI Optimization Methods. 3.2. Simulated Annealing. 3.3. Concluding Remarks. 4: Optimization Approach Based on Simulated Annealing. 4.1. Optimization Flow. 4.2. Problem Representation. 4.3. Perturbation Operators. 4.4. Acceptance and Generation Functions. 4.5. Temperature Schedule. 4.6. Stop Criterion. 4.7. Cost Function. 4.8. Concluding Remarks. 5: Efficient Algorithms and Data Structures. 5.1. Computational Model. 5.2. Asymptotic Analysis. 5.3. Computational Complexity. 5.4. Data Structures for CAD. 5.5. Concluding Remarks. 6: Placement. 6.1. Previous Work. 6.2. Effective and Efficient Placement. 6.3. Representation Generality, Flexibility and Sensitivity. 6.4. Sequence Pair Representation. 6.5. Graph-Based Packing Computation. 6.6.Non-Graph-Based Packing Computation. 6.7. Graph-Based Incremental Placement Computation. 6.8. Implementation Considerations. 6.9. Experimental Results. 6.10. Placement-to-Sequence-Pair Mapping. 6.11.Constrained Block Placement. 6.12. Concluding Remarks. 7: Routing. 7.1. The Routing Problem. 7.2. Classification of Routing Approaches. 7.3. Previous Work. 7.4. Computational Complexity. 7.5. Global Routing Model. 7.6. Global Routing Algorithms. 7.7. Benchmarking of Heuristics in Our Routing Model. 7.8. Incremental Routing. 7.9. Impact of Routing on Placement Quality. 7.10. Concluding Remarks. 8: Dealing with Physical Phenomena: Parasitics, Crosstalk and Process Variations. 8.1. Previous Work. 8.3. Self-Parasitics. 8.4. Crosstalk. 8.5. Process Variations. 8.6. Incorporating Crosstalk and Parasitics into Routing. 8.7. Incorporating Substrate Coupling into Placement. 8.8. Incremental Substrate Coupling Impact Minimization. 8.9. Concluding Remarks. 9: Conclusions. Bibliography. About the Authors. Index.

A gate array router that utilizes horizontal and vertical over-cell routing channels to increase cell density is described. Logic macros, with fixed intraconnect metal that may span several cell columns, are mapped onto the array producing partially filled routing channels. Macro interconnects are loosely assigned to the partially filled horizontal and vertical routing channels during global routing. Each loose horizontal channel segment is assigned to a channel track using a maze router. Vertical channel segments are completed by a modified dogleg channel router.

<p>Whole genome CNV landscape of PDX models profiled by ATAC-seq. A) ASCPs PAX139, PAX217, and PAX265. Vertical arrows highlight CDK6 amplicons and horizontal arrows highlight CDKN2A homozygous deletions. B) PDACs PAX295, PAX297, and PAX300. The X and Y axes in the CGH plots represent chromosome and log2 ratios for each genome. IGV views of ATAC-seq profiles of C) KRAS; D) MYC and ; E) CDK6 in ASCP (top rows) and PDAC (bottom rows) PDX models. F) Dose response profiles of PAX139 organoids to Palbociclib (left panel) and Abemaciclib (right panel). Organoids were seeded in 96-well plate coated with Matrigel (5,000 cells /well) in organoid media. After 2-3 days of growth, fresh organoid media and DMSO or drug (10 wells/condition) was added. Fresh media and drug was added every 2-3 days. MTT assay were done on day 7 to measure proliferation. The absorbance listed for each drug is the average of the 10 wells per condition. Each experiment was performed in triplicate.</p>

How cell numbers are determined is not understood. Hedgehog-Gli activity is involved in precursor cell proliferation and stem cell self-renewal, and its deregulation sustains the growth of many human tumours. However, it is not known whether GLI1, the final mediator of Hh signals, controls stem cell numbers, and how its activity is restricted to curtail tumourigenesis. Here we have altered the levels of GLI1 and p53, the major tumour suppressor, in multiple systems. We show that GLI1 expression in Nestin+ neural progenitors increases precursor and clonogenic stem cell numbers in vivo and in vitro. In contrast, p53 inhibits GLI1-driven neural stem cell self-renewal, tumour growth and proliferation. Mechanistically, p53 inhibits the activity, nuclear localisation and levels of GLI1 and in turn, GLI1 represses p53, establishing an inhibitory loop. We also find that p53 regulates the phosphorylation of a novel N' truncated putative activator isoform of GLI1 in human cells. The balance of GLI1 and p53 functions, thus, determines cell numbers, and prevalence of p53 restricts GLI1-driven stem cell expansion and tumourigenesis.

The objective of this chapter is two-fold. It is intended to review the basics of the MOS transistor, which is a prerequisite for Chapters 4. to 7., and to introduce commonly used models of both MOS and bipolar devices [Sections 3.1, 3.2, and 3.5]. In this chapter we consider simple analytical models which can be used for circuit analysis and design of deep-submicrometer MOSFET’s at low-voltage. Also, a simple model to compute the leakage current of MOSFET’s is presented [Section 3.3]. The more sophisticated SPICE device models are also presented to allow the reader to appreciate the meaning of the model parameters as well as the capabilities and limitations of these models. The SPICE parameters for the 0.8 µm CMOS/BiCMOS process presented in Chapter 2 are included in this chapter for readers who are interested in designing and simulating low-voltage CMOS circuits as well as BiCMOS circuits. In Section 3.4, supply voltage scaling due to reliability and power dissipation issues is presented.

Development of an electron cyclotron equatorial launcher has proceeded with a series of prototype tests and design enhancements intended to improve reliability and functionality of the launcher. The design enhancements include adaptation of the launcher steering angles such that one of three beam rows of the launcher is necessarily flipped to perform counter current drive to conform to a new ITER physics requirement. Also, the top and bottom steering rows have been tilted at an angle of 5 deg so that the top and bottom beam rows can be accessed from on-axis to near midradius. Furthermore, the position of the fixed focusing mirror that forms a quasi-optical in-vessel millimeter-wave (mm-wave) transmission line is modified to increase the nuclear shielding capability. A high-power experiment of the mm-wave launching system mock-up fabricated based on the design confirmed a successful steering capability of 20 to 40 deg. It was measured that some stray radio-frequency power propagated in the beam duct and generated some heat on the duct. Prototype tests also include the fabrication of the blanket shield module and partial port plug mock-up and have shown no serious technological issue regarding the fabrication and cooling functionality.

This paper proposes global routing models for capturing the impact of local congestion caused by varying-size vias. The models are then incorporated to dynamically drive a proposed layer assignment algorithm. A typical characteristic of advanced technology nodes is significantly high variation in wire sizes that may exist between adjacent metal layers. Routing from a global cell (g-cell) to its top metal layer results in using a via which may be up to twice the size of unit wire track within that g-cell. This results in significant decrease in the available routing tracks that could pass the boundaries of the g-cell. Ignoring this issue hampers the effectiveness of traditional global routing algorithms due to mismatch with the detailed routing stage. Based on these observations, we propose “via-aware edge overflow” and “edge-aware via overflow” models for capturing the impact of both unstacked and stacked vias of arbitrary sizes during global routing. Our models can be used to drive any layer assignment algorithm and replace the traditional edge overflow and via overflow metrics. To show the impact of our models, we also incorporate them in a proposed two-stage layer assignment algorithm and compare with a competitive layer assignment technique. This is also the first work to actually evaluate the impact of global routing solutions using a commercial detailed router. In our experiments we report fewer number of design rule check violations by only changing the layer assignment during global routing, and detail routing with Olympus-SoC of Mentor Graphics.

During the tailing current period when the bipolar device is turned off, plasma extraction transit time (PETT) oscillation will occur, and the electromagnetic interference caused by it will have a negative effect on the driver circuit and the surrounding electronic components. Therefore, it is necessary to investigate the factors that affect the characteristics of PETT oscillation. In this paper, the relationship between the characteristics of PETT oscillation and the operation conditions of high-voltage insulated gate bipolar transistor (IGBT) device is studied experimentally. When the DC link voltage, load current and gate driver resistance are changed, and the peak value and duration of PETT oscillation under different operation conditions are recorded. The results show that the PETT oscillation characteristics have a strong dependence on the voltage and current of IGBT device, as well as the gate driver resistance. The experimental results in this paper can provide the guidance for suppressing the PETT oscillation of high-voltage IGBT devices.

Experimental study of plate-buckling type earthquake-resilient prefabricated steel beam-column joints with replaceable double flange cover plates

In this paper, we present algorithms and experimental results for an automated layout synthesis procedure that is used in a high-level silicon compiler. The techniques consist of a unique approach to generalized cell synthesis, together with a novel solution of the placement and routing problem. Our algorithms take advantage of a larger space of possible solutions than is available in conventional, fixed-cell approaches to achieve compact and efficient layouts. First, our techniques for cell synthesis are presented. Then, we describe our placement algorithm, in which the locations of the cells are determined by signal-flow considerations. Next, our pin permutation procedure is described. These permutations are not limited to the relatively few cases of logically equivalent pins, but rather, can exploit a much larger set of transformations involving the re-arrangement of the inner structure of the cells themselves. Finally, our techniques for both global and channel routing are discussed. Experimental results for a complete chip layout are included.

This papers presents an implementation of a LEGAL algorithm following a previous established global routing. LEGAL algorithms were first proposed by Johann in 1994, where the ideas from the most efficient channel routing algorithms were combined and used to process detailed routing of large areas in almost linear time. Other implementations produced good detailed results but had no means of making a global routing distribution in bigger circuits, which is a task for global routing. Now we present the first implementation of a detailed LEGAL routing that can obey global paths previously chosen for each net. The mechanisms developed to isolate global and local decisions and still keep LEGAL routing being made over the whole area are the focus of this paper. The implementation should be tested and refined further to allow optimizations and become competitive to other approaches in practice.

A new methodology for hierarchical floor planning and global routing for building block layout is presented. Unlike the traditional approach, which separates placement and global routing into two consecutive stages, our approach accomplishes both jobs simultaneously in a hierarchical fashion. The global routing problem is formulated at each level as a series of the minimum Steiner tree problem in a special class of partial 3-trees, which can be solved optimally in linear time. The floor planner with a maximum of five rooms per level has been implemented in the C language, running on a VAX 8650 under 4.3 BSD UNIX. The experimental results on examples with a large number of irregular blocks show that our approach out-performs other well-known deterministic algorithms, and gives results that are comparable to random-based algorithms but with a computing time an order of magnitude less. Due to the unique goal-oriented and pattern-directed features of our floor planner, it accepts specifications for overall aspect ratio and I/O pad positions, thus making our approach suitable for hierarchical design.

Proposed in this paper is a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. The authors' approach provides a general framework that may use any single-net routing algorithm and any delay model in global routing. It is based on the observation that there are several routing topology flexibilities that can be exploited for congestion reduction under timing constraints. These flexibilities are expressed through the concepts of a soft edge and a slideable Steiner node. Starting with an initial solution where timing-driven routing is performed on each net without regard to congestion constraints, this algorithm hierarchically bisects a routing region and assigns soft edges to the cell boundaries along the bisector line. The assignment is achieved through a network flow formulation so that the amount of timing slack used to reduce congestions; is adaptive to the congestion distributions. Finally, a timing-constrained rip-up-and-reroute process is performed to alleviate the residual congestions. Experimental results on benchmark circuits are quite promising and the run time is between 0.02 s and 0.15 s per two-pin net.

As technology advances, interconnection wires are placed in closer proximity and circuits operate at higher frequencies. Consequently, reduction of crosstalk between interconnection wires becomes an important consideration in VLSI design. In this paper, we study the gridded channel routing problem with tbe objective of satisfying crosstalk constraints for the nets. We proposed a new approach to the problem which utilizes existing channel routing algorithms and improves upon the routing results by permuting the routing tracks. The permutation problem is proven to be NP-complete. A novel mixed ILP formulation and effective procedures for reducing the number of variables and constraints in the mixed ILP formulation are then presented. The new algorithm is tested on three large benchmark circuits as well as many randomly generated circuits. The experimental results are very promising.