Auxiliary qubit selection: a physical synthesis technique for quantum circuits

Optimizations developed in earlier chapters affect many aspects of physical synthesis, but often target sequential elements, which particularly impact circuit performance. In order to obtain synergies between these optimizations, we explore the infrastructure for physical synthesis used by IBM for large commercial microprocessor designs. We focus our attention on a very challenging high-performance design style called large-block synthesis (LBS). In such designs latch placement is critical to the performance of the clock network, which in turn affects chip timing and power. Our research uncovers deficiencies in the state-of-the-art physical synthesis flow vis-à-vis latch placement that result in timing disruptions and hamper design closure. We introduce a next-generation EDA methodology that improves timing closure through careful latch placement and clock-network routing to (i) avoid timing degradation where possible, and (ii) immediately recover from unavoidable timing disruptions. When evaluated on large CPU designs recently developed at IBM, our methodology leads to double-digit improvements in key circuit parameters, compared to IBMs prior state-of-the-art methodologies.KeywordsSlew RateTiming DegradationCombinational LogicPlacement AlgorithmLogic SynthesisThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Interconnect delays represent an increasingly dominant portion of overall circuit delays. During timing-driven physical synthesis process, timing analysis is repeatedly performed over several hundred thousand components. Thus, fast and accurate estimation of interconnect delays is crucial. Traditionally, lumped and elmore delay models have been widely used for computing interconnect delays in physical synthesis due to their computational efficiency. However, these delay models are known to be inaccurate since they ignore slew and resistive shielding effects. In this paper, we propose a new iterative refinement based delay estimation approach that considers resistive shielding along with driver slew. Experimental results show that the proposed approach gives not only highly accurate results for far end RC-line delays but also compares very favorably to more difficult to match source end delays and source slews. In addition, use of the proposed delay model in physical synthesis yields significant performance improvement on several large industrial ASICs.

On behalf of the organizing committee, we would like to welcome you to the 9th International Workshop on System-Level Interconnect Prediction (SLIP'07), held on March 17-18, 2007 at the Dolce Lakeway Resort and Spa in Austin, Texas. The SLIP workshop focuses on modeling and prediction of usable properties of optimized interconnect systems and their impact on system performance. Both theory and applications of interconnect prediction techniques are highlighted, with emphasis on applications to architectural and micro-architectural exploration, physical design, interconnect technology planning, and communication networks. In addition to the presentation of state-of-the-art papers in these fields, invited talks and tutorials by leading researchers aim to encourage dialogue between the architecture, physical design, and interconnect technology communities. Following a rigorous review process, the program committee has selected an outstanding set of 12 papers for publication in the proceedings and oral presentations at the workshop. The topics of selected papers cover a wide range of issues, including impact of new materials (e.g., low-k dielectrics, carbon nanotube bundles) on interconnect performance, congestion estimation and early interconnect characterization and planning, and the impact of process variation on interconnect performance. In addition to the contributed papers, we continue the SLIP tradition of featuring in the technical program several distinguished invited speakers. This year Avinoam Kolodny from Technion will speak about networks on chips, Majid Sarrafzadeh from UCLA will give a tutorial on congestion prediction, and Charles Alpert from IBM Austin Research Laboratory will speak on physical synthesis.

An accurate model is presented for the prediction of physical design characteristics, such as interconnection lengths and layout areas, for standard cell layouts. This model produces accurate shape constraint functions (height versus width of the layout over a range of aspect ratios) by considering the logic design specification, the physical design process, and the physical implementation technology. Random and optimized placements, global and detailed routing are each abstracted by procedural models that capture the important features of these processes. Equations that define the procedure model are presented. Predictions of layout characteristics that are within 10% of the actual layouts are achieved over a range of circuit functions and sizes. The authors have verified both the global characteristics (total interconnection length and layout area) and the detailed characteristics (wire length and feedthrough distributions) of the model. Accurate prediction of physical design characteristics is useful for floorplanning, evaluating the fit of a logic design to a fabrication technology, and studying placement algorithms. >

During the physical design process, prior to detailed routing, it is desired to bound the interconnect delay based on the bounding box of the pins on the net, horizontal, and vertical estimates of interconnect capacitance and resistance per length and estimate the pin-to-pin delays based on the positions of the pins inside and on the bounding box. Assuming the interconnect will be routed based on a rectilinear Steiner tree (RST), the work of F.K. Chung and F.H. Hwang (1979) is used to bound the size of the largest and smallest possible RSTs given the bounding-box of the pins on the net (this is done for nets with >

Rapid advancement in the domain of quantum technologies have opened up researchers to the real possibility of experimenting with quantum circuits, and simulating small-scale quantum programs. Nevertheless, the quality of currently available qubits and environmental noise pose a challenge in smooth execution of the quantum circuits. Therefore, efficient design automation flows for mapping a given algorithm to the Noisy Intermediate Scale Quantum (NISQ) computer becomes of utmost importance. State-of-the-art quantum design automation tools are primarily focused on reducing logical depth, gate count and qubit counts with recent emphasis on topology-aware (nearest-neighbour compliance) mapping. In this work, we extend the technology mapping flows to simultaneously consider the topology and gate fidelity constraints while keeping logical depth and gate count as optimization objectives. We provide a comprehensive problem formulation and multi-tier approach towards solving it. The proposed automation flow is compatible with commercial quantum computers, such as IBM QX and Rigetti. Our simulation results over 10 quantum circuit benchmarks, show that the fidelity of the circuit can be improved up to 3.37 × with an average improvement of 1.87 ×.

This work contains the analysis of results received after running synthesized quantum circuits for training perceptron neural networks. The training is performed by creating a Grover's algorithm with a custom oracle function. The concept of synthesizing quantum circuits was showcased in the process of generating training circuits for three perceptron topologies, which were designed to test the accuracy of the synthesis process. The test circuits serve to prove that the proposed synthesis approach could be scaled to utilize more complex quantum computing systems and to solve more practical tasks. IBM's 100-qubit cloud quantum simulator was used as the debugging environment. Quantum circuits for described algorithms are generated by the "Naginata" quantum synthesizer, its source code is published and further documented on GitHub along with the code for the provided example algorithms. The article describes the processes behind the algorithm for synthesizing quantum circuits that perform the training process of single-layer perceptrons by finding their weights by filtering all possible input values through a predefined accuracy criterion. Since quantum computing is still in its early development phase, quantum circuits are created mainly by manual placement of logic elements. Implementing quantum algorithms, especially more use-case specific ones, directly on the quantum circuit level could lead to the circuit easily becoming too complex for human comprehension. Quantum Circuit Synthesizer "Naginata" was created to simplify the development and debugging process of quantum algorithms, by adding better clarity to their development process. In our case, better clarity for the development process is achieved by composing functions for commonly used operations performed in the implemented quantum algorithm. The programmer could now implement the quantum algorithm as a set of functions, instead of manually creating a circuit from single logic elements. After this, the synthesizer would handle the task of creating the data for placing logic elements on the circuit. This enables an opportunity of implementing quantum algorithms with higher-level commands. In the scope of this work, parametrically generated generic blocks for frequently used operations such as: the adder, multiplier and digital comparator were created and utilized to form the training circuits. The test results, proved that with the help of the proposed quantum synthesizer, these compositions could be used efficiently as building blocks for implementing quantum algorithms. And by visually comparing sizes of both code and circuit representations of the synthesized circuits, to the code examples used to synthesize these circuits, it is determined that the proposed approach for implementing quantum circuits greatly simplifies the processes of development and debugging a quantum algorithm.

Quantum computation can solve certain problems much faster than classical computation. However, quantum computations are more susceptible to errors than conventional digital computations. Thus, a fault-tolerant (FT) quantum circuit design is required for a practical implementation. Quantum circuits consist of a cascade of quantum gates. These gates are themselves realized using primitive quantum operations that are supported by the quantum physical machine description (PMD). As different quantum systems are associated with different Hamiltonians, they have different PMDs. In addition, the quantum cost for implementing a quantum operation may differ from one PMD to another. Thus, a quantum logic circuit needs to be realized with and optimized for the set of primitive quantum operations supported by the given PMD. In this paper, an FT quantum logic synthesis (FTQLS) methodology and tool is described for six different PMDs. A methodology, such as this, which can be targeted at multiple PMDs, has not been attempted before, to the best of our knowledge. The input to FTQLS is an unoptimized quantum circuit realized using a set of commonly used gates and its output is an optimized FT quantum circuit that only comprises of primitive quantum operations supported by the given PMD. FTQLS does technology mapping for different PMDs and then converts non-FT circuits to FT circuits. For technology mapping, it utilizes an optimized quantum gate library targeted at various PMDs that decomposes gates into primitive operations. Efficient conversion to FT circuits is done by integrating two quantum compilers and an FT cache table into FTQLS. For improving the synthesis results, an FT set of gates that is directly supported by each PMD is proposed. Quantum circuit optimization is done by utilizing quantum identity rules. The performance of FTQLS is evaluated using two cost metrics: number of primitive operations (#ops) and execution cycles on the critical path (#cycles). Experiment results show that the decrease in #ops varies between 58.1% and 87.0% and in #cycles between 42.8% and 76.4%, on an average, depending on the PMD.

Advancements in silicon photonics technology are enabling large scale integration of electro-optical circuits and systems. To fully exploit this potential, automated techniques for design space exploration and physical synthesis for integrated optics must be developed. This paper investigates how conventional VLSI physical design automation techniques can be adapted for integrated optics applications. We present an overall methodology for cell-placement, global routing, and detail routing for physical synthesis of optical circuits. In addition, we highlight optics-specific constraint models, design rules and optimization criteria that will have to be accounted for in physical design automation.

When RTL designers define the hierarchy of a system, they exploit their knowledge about the conceptual abstractions devised during the design and the functional interactions between the logical components. This valuable information is often lost during physical synthesis. This article proposes HiDaP, a novel multilevel algorithm that uses RTL information and analytical methods for the macro placement problem of modern designs dominated by multicycle connection pipelines. By taking advantage of the hierarchy tree, the netlist is divided into blocks containing macros and standard cells, and their dataflow affinity is inferred considering the register latency and flow width of their interaction. The layout is represented using slicing structures and generated with a top-down algorithm capable of handling blocks with both hard and soft components. An adaptive multiobjective cost function is used to simultaneously minimize wirelength, timing, overlap, and distance to preferred locations, which can be user defined or generated by analytic methods (spectral and force directed). These techniques have been applied to a set of large industrial circuits and compared against state-of-the-art commercial and academic placers, and also to handcrafted floorplans generated by expert backend engineers. The proposed approach outperforms previous algorithmic methods and can produce solutions with better wirelength and timing than the best handcrafted floorplans. Post-routing layouts are almost brought to timing closure and DRC cleanness with minimal engineer modification, showing that the generated floorplans provide an excellent starting point for the physical design flow and contribute to reduce turn-around time significantly.

This paper explores the foundational concepts for the application of Quantum Machine Learning (QML) algorithms on photovoltaic (PV) array fault detection. Our study leverages in a unique manner quantum entanglement to enhance classification accuracy. We introduce new parameterized quantum circuit designs that enable flexible training and efficient feature encoding. We propose a novel approach utilizing quantum entanglement and quantum data correlation to encode complex relationships among PV features. This method enables the detection of subtle and correlated PV fault patterns. In addition, this approach highlights the potential of quantum systems to capture dependencies within data that are more challenging in classical computing models. In the designed quantum circuits, we show that as the number of entangling gates (two-qubit gates) grows, quantum entanglement can reveal data correlation. Simulation results examine the role of quantum data correlation in optimizing the classification process. Additionally, the scalability of entangled quantum circuits as the number of qubits increases is studied, along with the properties of quantum data correlation and its benefits in classification. The contributions presented in this paper are: a) the design of new quantum circuits that leverage correlation, b) the observation of a quantum state under different fault detection conditions, c) the capability to classify accurately among four different PV faults, and d) demonstration of accuracy improvement of about 10% over our previous study.

Quantum Computing has been evolving in the last years. Although nowadays quantum algorithms performance has shown superior to their classical counterparts, quantum decoherence and additional auxiliary qubits needed for error tolerance routines have been huge barriers for quantum algorithms efficient use.These restrictions lead us to search for ways to minimize algorithms costs, i.e the number of quantum logical gates and the depth of the circuit. For this, quantum circuit synthesis and quantum circuit optimization techniques are explored.We studied the viability of using Projective Simulation, a reinforcement learning technique, to tackle the problem of quantum circuit synthesis. The agent had the task of creating quantum circuits up to 5 qubits. Our simulations demonstrated that the agent had a good performance but its capacity for learning new circuits decreased as the number of qubits increased.

Faster manipulation of large quantum circuits using wire label reference diagrams

Realizing the promised advantage of quantum computers over classical computers requires both physical devices and corresponding methods for the design, verification and analysis of quantum circuits. In this regard, decision diagrams have proven themselves to be an indispensable tool due to their capability to represent both quantum states and unitaries (circuits) compactly. Nonetheless, recent results show that decision diagrams can grow to exponential size even for the ubiquitous stabilizer states, which are generated by Clifford circuits. Since Clifford circuits can be efficiently simulated classically, this is surprising. Moreover, since Clifford circuits play a crucial role in many quantum computing applications, from networking, to error correction, this limitation forms a major obstacle for using decision diagrams for the design, verification and analysis of quantum circuits. The recently proposed Local Invertible Map Decision Diagram (LIMDD) solves this problem by combining the strengths of decision diagrams and the stabilizer formalism that enables efficient simulation of Clifford circuits. However, LIMDDs have only been introduced on paper thus far and have not been implemented yet—preventing an investigation of their practical capabilities through experiments. In this work, we present the first implementation of LIMDDs for quantum circuit simulation. A case study confirms the improved performance in both worlds for the Quantum Fourier Transform applied to a stabilizer state. The resulting package is available under a free license at https://github.com/cda-tum/ddsim/tree/limdd .

ABSTRACTQuantum computing environments make block ciphers susceptible to exhaustive key search attacks utilizing Grover's algorithm. However, such quantum‐based attacks remain impractical unless the targeted cipher is directly implemented on a quantum platform. Moreover, their efficiency significantly depends on the quantum circuit design and optimization of the block cipher in question. The cost of a quantum circuit implementation is typically measured by two main metrics: the number of qubits and the circuit depth (T‐depth). For most block ciphers, the S‐box is the principal factor contributing to increased T‐depth and additional qubit requirements. This paper presents a method for generating quantum circuits directly from lookup tables of S‐boxes applicable to arbitrary block ciphers. We illustrate our approach using quantum circuit implementations of the PRESENT and DES ciphers as practical examples. Our proposed method is expected to efficiently implement arbitrary S‐boxes by employing polynomial evaluation, thus balancing time–space complexity.