Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism

Nowadays System on Chip (SoC) is expected to perform a large number of applications as per the requirement of customers. Increase in the number of applications leads to an increase in the number of cores inside the SoC. Customers want to use a large number of applications in their product but in a cheap price. In this price competitive market, the manufacturer can not increase the price above a certain range in order to sustain in the market. It is decisive to have a high-quality product with the low price. Testing each core thoroughly can require high amount of time and increases the test economics. Hence it is better to cover significant faults only and test the cores partially. In this paper, we propose a method for incomplete testing of the SoC cores, which recedes Test Power (TP) and Test Data Volume (TDV). Our method persists significant fault coverage and tests most of the significant faults. We also propose a power aware Test access mechanism (TAM) architecture compatible with the reduced test vectors. It provides a trade-off between quality of product and testing parameters (i.e., TP, TDV). Results from experiments exhibit an effective reduction in TDV, TP with a nominal compromise on the quality of testing.

This paper proposes a new parallel test access strategy for multiple identical cores in a network-on-chip (NoC). The proposed test strategy takes advantage of the regular design of NoC to reduce both test area overhead and test time. The proposed NoC reused test access mechanism (TAM) adopted a pipelining structure and a deterministic test data routing algorithm in order to reuse the full bandwidth of links in the NoC. Also, the architecture has complete scalability according to the number of cores and applications for 3D environment are also represented. Experimental results show that the proposed TAM can test multiple cores with the same test time as a single core and negligible hardware overhead.

Test access mechanism (TAM) optimization and test data compression lead to a reduction in test data volume and testing time for SOCs. In this paper, we integrate for the first time both these approaches into a single test methodology. We show, how an integrated test architecture based on TAMs and test data decoders can be designed. The proposed approach offers considerable savings in test resource requirements. Two case studies using the integrated test architecture are presented. Experimental results on rest data volume reduction, savings in test application time and the low test pin overheads for a benchmark SOC demonstrate the effectiveness of this approach.

In this paper, a new algorithm for reformatting the test vector of system on chip (SOC) with test access mechanism (TAM) has been proposed. Exhaustive experimentation has been conducted by employing random reformatted test vectors for a variety of SOCs, constructed with the ISCAS sequential benchmark circuits. For a limited number of input pins, which have been provided for testing the SOC, the proposed algorithm drastically reduces the test-time as well as the hardware.

We propose a technique to integrate core selection in the SOC (system-on-chip) test solution design-flow. It can, in contrast to previous approaches, be used in the early design-space exploration phase (the core selection process) to evaluate the impact on the system's final test solution imposed by different design decisions, i.e. the core selection and the cores' test characteristics. The proposed technique includes the interdependent problems: test scheduling, TAM (test access mechanism) design, test set selection and test resource floor-planning, and it minimizes a weighted cost-function based on test time and TAM routing cost while considering test conflicts and test power limitations. An advantage with the technique is the novel three-level power model: system, power-grid, and core. We have implemented and compared the proposed technique, a fast estimation technique and a computational extensive pseudo-exhaustive method, and the results demonstrate that our technique produces high quality solutions at reasonable computational cost.

We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of test resources (e.g., test access mechanisms (TAM)), we determine the test plan for the application of the tests to the SOC. Test planning in this paper refers to the combined activities of test access architecture partitioning and test scheduling. These activities must be performed in conjunction as the choice of the test access architecture influences the test schedule. We justify the formulation of test scheduling w.r.t. minimum average completion time criterion as compared to minimum makespan. We show that then the problem of scheduling tests on TAMs can be mapped onto a graph theoretic problem which has a polynomial time optimal solution. We have implemented our algorithm as a test planner tool TPLAN. We present the theoretical analysis of our approach in this paper, and compare our results against those published earlier using integer linear programming techniques with encouraging results.

The test scheduling problem is one of the major issues in the test integration of system-on-chip (SOC), and a test schedule is usually influenced by the test access mechanism (TAM). In this paper we propose a graph-based approach to power-constrained test scheduling, with TAM assignment and test conflicts also considered. By mapping a test schedule to a subgraph of the test compatibility graph, an interval graph recognition method can be used to determine the order of the core tests. We then present a heuristic algorithm that can effectively assign TAM wires to the cores, given the test order. With the help of the tabu search method and the test compatibility graph, the proposed algorithm allows rapid exploration of the solution space. Experimental results for the ITC02 benchmarks show that short test length is achieved within reasonable computation time.

This work presents a new dynamically configurable compression architecture to be integrated directly into the test access mechanism of System-on-Chip (SoC) designs using IEEE 1149 compliant interfaces. The proposed technique reduces the test data volume without loosing the full legacy support, no extra IO pins are needed and the additional allocated hardware resources are negligible. Particularly, this technique is suitable for board as well as in-field testing, which both use typically a Test Access Mechanism (TAM) like IEEE 1149. Here, strong memory limitations exist on the test equipment, which restrict the testing or debugging capabilities for complex designs. Various benchmarks for random test data, representing highly pre-compressed test data, as well as fully-specified test data for selected industrial circuit designs were run and discussed to evaluate this new approach. These experiments clearly show a high test data volume reduction. Additionally, a noticeable reduction of the overall number of required test cycles are achieved for most of the test cases.

System on a chip (SOC) based on reusable IP core has been widely used in integrated circuit (IC) design and manufacturing. However SOC efficient test is still the bottle-neck issue. Test scheduling can enhance parallel test to minimize test application time at SOC system level. We present a modified differential evolution (MDE) approach to solve the problems of test scheduling and test access mechanism (TAM) partition for system on chips. A new hybrid mutation mechanism based on the probability estimation operator is introduced in the paper for better handling test scheduling, where the first variation coefficient stays the same but the second variation coefficient changes with iterative times. The different evolutionary strategies are adopted to accelerate effectively convergence without loss in population diversity as far as possible. Different mutation operators and evolutionary strategies are combined to get optimal results. The experimental results on ITC'02 SOC benchmarks are encouraging compared with the improved quantum-inspired evolutionary (IQI), genetic algorithm (GA), the integer linear programming formulation (ILP) and heuristic approaches.

With the increase of the number of IP cores integrated in SOC, the functions of SOC ar e becoming more complexed. Test time and test cost grow rapidly, therefore it becomes bo ttleneck of SOC test. Test scheduling is one of the efficient approaches to solve the forenamed ques tion. Cross-entropy method, which is ba sed on probability density function, has been used to solve the SOC test scheduling problem. Experimental results on ITC’02 benchmarks show that the proposed method provides better test time results compared to the Linear-Programming. Keywords: System on chip, test scheduling, cross-entropy method 1. INTRODUCTION In order to shorten the time to market, core based system-on-chip (SOC) design has becomed a widely used technique of integrated circuit design. Compared with system-on-board, work frequency of SOC has improved observably because signal transfers delay is avoid. However, the testing of SOC and the reusable cores becomes a bottleneck of the SOC development. The SOC test includes test information exchange mechanism, test wrapper generation, test access mechanism (TAM) design, test controller design, test schedulin g and test integration, etc. Among the SOC test issues, the test scheduling is one of the most important challenges. Many works have forced on core test scheduling to minimize the overall testing time, in [7], the test scheduling is mapped to the linear programming (LP) problem, but the computation time is too long. In this paper, we use a cross-entropy (CE) method, which is based on probability density function, to solve the test scheduling problem. The paper is organized as follows. In section II, the test scheduling problem is briefly described. We formulate the problem of test scheduling using CE method in section III. Experimental results are given in section IV, and section V concludes the paper.

A novel test controller architecture is presented that allows multiple IEEE 1500 wrapped cores within a SoC to be tested concurrently. The IEEE 1149.1 state machine is used to interface to the test controller allowing potential integration with the emerging IEEE P1687 (IJTAG) standard. Also included is a test access mechanism (TAM) methodology that reuses the physical connections of the SoC system bus to provide an efficient transport medium for test vectors between the test controller and IEEE 1500 wrapped cores.

Test access is a major problem in testing embedded cores as it directly impacts testing time and hardware cost. Test access mechanism (TAM) is responsible for test data transport and is characterized by its bandwidth capacity. Efficient TAM design is of critical importance in SOC system integration since a test architecture should reduce test cost by minimizing test application time. In this paper, we propose a genetic algorithm to design test access architectures while investigating test bus sizing concurrently with assigning cores to test buses. We present experimental results that demonstrate the effectiveness of the proposed method.

A novel test access mechanism (TAM) architecture with multi test-channel (TC) based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip (SoC) test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC’02 test benchmark.

Intellectual property (IP) cores reused technology improves system-on-a-chip (SoC) design productivity. However, with more IP cores embedded in the deeper levels, the hierarchical architecture of SoC becomes complex, which also makes the test difficult. A scan chains combined-balance (SCCB) strategy is proposed in this paper to reconfigure and balance the scan chains, which helps reduce test time and overhead. The SCCB strategy is different from the traditional test method, wherein the test access mechanism (TAM) and Scheduling are established as a virtual flattened form. We take experiments to verify the SCCB strategy based on the ITC'02 benchmarks. The experimental results show that the SCCB strategy is effective.

Low-power multi-core ATPG to target concurrency