A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System

The increased usages of multi-core systems diminish per-core complexity and also demand several parallel design and test technologies. This paper introduces a novel test access mechanism (TAM) for parallel testing of multiple identical cores. Instead of typical test response data from the cores, the test output data used in this paper are the majority values extracted from the typical test response from the cores. All the cores can be tested in parallel and test costs (test time, test pins) are exactly the same as for a single core. The experiment results in this paper show the proposed TAM can test multiple cores with minimal test pins and test time and with negligible hardware overhead.

Test data travels through a System-on-Chip (SOC) from the chip pins to the module-under-test and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented with dedicated wires. However, also existing functional interconnect, such as a bus or Network-on-Chip (NOC), can be reused as TAM. This will reduce the overall design effort and the silicon area. For a given module, its test set, and maximal bandwidth that the functional interconnect can offer between ATE and module-under-test, our approach designs a test wrapper for the module-under-test such that the test length is minimized. Unfortunately, it is unavoidable that with the test data also unused (idle) bits are transported. This paper presents a TAM bandwidth utilization analysis and techniques for idle bits reduction, to minimize the test length. We classify the idle bits into four types which explain the reason for bandwidth under-utilization and pinpoint design improvement opportunities. Experimental results show an average bandwidth utilization of 80%, while the remaining 20% is consumed by the idle bits.

Network on Chip (NoC) is an emerging interconnect solution with reliable and scalable features over the System on Chip (SoC) and helps to overcome the drawbacks of bus-based interconnection in SoC. The multiple cores or other networks have a boundary which is limited to communicate with devices, which are directly connected to it. To communicate with these multiple cores outside the boundary, the NOC requires the gateway functionality. In this manuscript, a cost-effective Network Gateway (NG) model is designed, and also the interconnection of a network gateway with multiple cores are connected to the NoC based system is prototyped on Artix-7 FPGA. The NG mainly consists of Serializer and deserializer for transmitting and receiving the data packets with proper synchronization, temporary register to hold the network data, electronic crossbar switch is connected with multiple cores which are controlled by switch controller. The NG with the Router and different sizes of NoC based system is designed using congestion-free adaptive-XY routing. The implementation results and performance evaluation are analyzed for NG based NoC in terms of average Latency and maximum Throughput for different Packet Injection Ratio (PIR). The proposed Network gateway achieves low latency and high throughput in NoC based systems for different PIR.

Testing NoC-based systems mainly relies on reusing the Network-on-Chip architecture as the test access mechanism (TAM). This, however, implies that the core's test wrapper is supplied with full NoC channel width even if there is a mismatch between the two. How to effectively and efficiently make better utilization of the NoC channels for test data transferring is therefore an interesting and challenging problem. In this paper, we propose to combine a new wrapper design with interleaved test scheduling. Compared to [8], the proposed method can achieve better NoC channel utilization for test without manipulating test frequencies, which not only reduces test power, but also saves design effort for the test engineers. Consequently, the testing time of the NoC-based system is considerably reduced with the proposed technique (especially under stringent power constraints), as shown in the experimental results on circuits crafted from ITC02 benchmarks.

Test access is a major problem in testing embedded cores as it directly impacts testing time and hardware cost. Test access mechanism (TAM) is responsible for test data transport and is characterized by its bandwidth capacity. Efficient TAM design is of critical importance in SOC system integration since a test architecture should reduce test cost by minimizing test application time. In this paper, we propose a genetic algorithm to design test access architectures while investigating test bus sizing concurrently with assigning cores to test buses. We present experimental results that demonstrate the effectiveness of the proposed method.

We propose a technique to integrate core selection in the SOC (system-on-chip) test solution design-flow. It can, in contrast to previous approaches, be used in the early design-space exploration phase (the core selection process) to evaluate the impact on the system's final test solution imposed by different design decisions, i.e. the core selection and the cores' test characteristics. The proposed technique includes the interdependent problems: test scheduling, TAM (test access mechanism) design, test set selection and test resource floor-planning, and it minimizes a weighted cost-function based on test time and TAM routing cost while considering test conflicts and test power limitations. An advantage with the technique is the novel three-level power model: system, power-grid, and core. We have implemented and compared the proposed technique, a fast estimation technique and a computational extensive pseudo-exhaustive method, and the results demonstrate that our technique produces high quality solutions at reasonable computational cost.

NoC (Network on Chip) is an emerging paradigm for design of VLSI/ULSI circuits to overcome communication bottleneck of traditional bus based systems. NoC communication framework consists of regularly placed routers, which are connected to processing cores. NoC performance is determined by latency and throughput for communication requirements. NoC communication traffic modelling plays an important role in design of NoC simulators and/or prototypes. This paper presents a framework for modelling source traffic for multipoint communication from one source to different destinations as is required for multicasting. Such a traffic model captures real-world scenarios such as multicasting, execution of concurrent multiple tasks on a single core (each task requiring communication with different destinations). The model proposes how concurrent traffic streams from a single core to different destinations can be mathematically characterized as a single stream at source end. The model is derived from statistical behaviour of probabilistically demultiplexing of a single traffic stream. In its nascent stage, the method is proposed for a scenario of one source concurrently communicating with two destinations as shall be required for mapping two concurrent tasks to same core or simultaneous broadcast to two destinations.

In this paper, we present a novel routing algorithm in order to avoid deadlock and packet dropping. In our proposed algorithm the network-on-chip (NoC) is capable of tolerating faults in presence of control faults in combinational parts of routers. In addition, by modifying the functionality of the router, the router is enabled to test its own, as well as the preceding router's functionality based on the routing algorithm, destination address and previous router's situation. Each router recognizes the faulty neighbor and announces it to successive routers. In this scheme no extra packets will be generated. We analyze the effects of our method on latency, power consumption and drop rate. Our experimental results illustrate that, fault coverage for routers can reach up to 100% with yet low power consumption and significant improvement in latency compared to the baseline approach.

With the increase of the number of IP cores integrated in SOC, the functions of SOC ar e becoming more complexed. Test time and test cost grow rapidly, therefore it becomes bo ttleneck of SOC test. Test scheduling is one of the efficient approaches to solve the forenamed ques tion. Cross-entropy method, which is ba sed on probability density function, has been used to solve the SOC test scheduling problem. Experimental results on ITC’02 benchmarks show that the proposed method provides better test time results compared to the Linear-Programming. Keywords: System on chip, test scheduling, cross-entropy method 1. INTRODUCTION In order to shorten the time to market, core based system-on-chip (SOC) design has becomed a widely used technique of integrated circuit design. Compared with system-on-board, work frequency of SOC has improved observably because signal transfers delay is avoid. However, the testing of SOC and the reusable cores becomes a bottleneck of the SOC development. The SOC test includes test information exchange mechanism, test wrapper generation, test access mechanism (TAM) design, test controller design, test schedulin g and test integration, etc. Among the SOC test issues, the test scheduling is one of the most important challenges. Many works have forced on core test scheduling to minimize the overall testing time, in [7], the test scheduling is mapped to the linear programming (LP) problem, but the computation time is too long. In this paper, we use a cross-entropy (CE) method, which is based on probability density function, to solve the test scheduling problem. The paper is organized as follows. In section II, the test scheduling problem is briefly described. We formulate the problem of test scheduling using CE method in section III. Experimental results are given in section IV, and section V concludes the paper.

Test access mechanism (TAM) optimization and test data compression lead to a reduction in test data volume and testing time for SOCs. In this paper, we integrate for the first time both these approaches into a single test methodology. We show, how an integrated test architecture based on TAMs and test data decoders can be designed. The proposed approach offers considerable savings in test resource requirements. Two case studies using the integrated test architecture are presented. Experimental results on rest data volume reduction, savings in test application time and the low test pin overheads for a benchmark SOC demonstrate the effectiveness of this approach.

Currently, FPGAs serve as Field-Programmable-Systems-on-Chip (FPSoCs) and are widely used to implement computationally intensive real world applications. As the number of components in FPSoCs increase, the interconnect schemes based on Network-on-Chip (NoC) approach are increasingly being used to overcome the deficiencies of the traditional bus- based and point-to-point interconnect schemes. The router is a key component that greatly impacts the performance and cost of an NoC. In this paper we present FLNR, a fast light-weight NoC router designed for FPGAs. It is a 5-port packet switched wormhole router that uses a deterministic XY Routing algorithm and round robin arbitration scheme. The size of the input buffers and the flit size are parameterizable. We used novel techniques to achieve good speed performance while minimizing the area used. The number of control fields in a packet is minimized to reduce the size of buffers used. Credit based flow control is used to reduce the number of clock cycles required for transferring each flit. Both edges of the clock are used to implement router operations thereby speeding up the router. FLNR is compared to other proposed routers based on three metrics: area, frequency and zero load latency. Synthesis results and zero load latency evaluations show that our router is significantly superior to widely referenced, previously proposed routers.

In this paper, a test access mechanism named TESTLINE and its test time and power optimization algorithm for SOC test is presented. TESTLINE just needs 5 pins and can provide high-speed parallel test scheme. TESTLINE has a scalable mechanism. Its schematic can be easily configured according to test time and test power. ILP (Integer Linear Programming) is used to find the optimal results. TESTLINE also is a hierarchical structure. It is easy to build a hierarchical test access mechanism.

A novel test access mechanism (TAM) architecture with multi test-channel (TC) based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip (SoC) test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC’02 test benchmark.

Test scheduling is an important task for the test of a system on chip, and it determines the assignment of cores to the test access mechanism such that the overall test time is minimized. A new test scheduling approach based on cultural algorithms for system on chip is presented in this paper. First of all, the optimization model of test scheduling is given, the model uses the information such as the bits width of the test access mechanism and the scale of test sets of cores, the crosstalk fault test sets of core interconnect lines is also discussed. Secondly, a method based on cultural algorithms is proposed to solve the optimization model of test scheduling. The ant colony algorithm is used in the population space, and the conventional genetic algorithm is used in the belief space. The feasible solutions of test scheduling are represented by individuals, a lot of individuals form the populations. The optimal test scheduling scheme is obtained by the evolution of the populations. Experimental results on a lot of benchmark circuits show that the proposed approach in this paper can solve the problem of test scheduling effectively.

Previous work on testing NoC-based systems has shown that the integrated network can be efficiently reused as test access mechanism (TAM). These approaches exploit the given infrastructure for data transportation. Beyond that, NoC-architectures for nanoscale systems also have to ensure a reliable communication by additional hardware and/or software measures. For example a cyclic redundancy check (CRC) may be added to protect the end-to-end communication between network resources. This paper presents an approach to reuse the CRC hardware for a compression scheme similar to LFSR-reseeding. The experimental results show that competitive compression ratios can be achieved at low extra cost. This way, core testing in NoC-based systems can benefit from test data compression even for standard cores without integrated decompressors.