A scalable test mechanism and its optimization for test access to embedded cores

This paper proposes a new parallel test access strategy for multiple identical cores in a network-on-chip (NoC). The proposed test strategy takes advantage of the regular design of NoC to reduce both test area overhead and test time. The proposed NoC reused test access mechanism (TAM) adopted a pipelining structure and a deterministic test data routing algorithm in order to reuse the full bandwidth of links in the NoC. Also, the architecture has complete scalability according to the number of cores and applications for 3D environment are also represented. Experimental results show that the proposed TAM can test multiple cores with the same test time as a single core and negligible hardware overhead.

This paper discusses the extensions to the automatic SOC test architecture optimization tool TR-ARCHITECT that allow the user to partially specify the resulting test architecture. We describe a novel Test Architecture Specification (TAS) language, in which the user can express constraints with respect to (1) the number of Test Access Mechanisms (TAMs), (2) the TAM widths, (3) the assignment of modules to TAMs, and (4) the module ordering within a TAM. We also describe the extensions and modifications to the algorithms of TR-ARCHITECT that were necessary to incorporate the ability to satisfy the user constraints. We present experimental results for several ITC'02 SOC Test Benchmarks.

Test access is a major problem in testing embedded cores as it directly impacts testing time and hardware cost. Test access mechanism (TAM) is responsible for test data transport and is characterized by its bandwidth capacity. Efficient TAM design is of critical importance in SOC system integration since a test architecture should reduce test cost by minimizing test application time. In this paper, we propose a genetic algorithm to design test access architectures while investigating test bus sizing concurrently with assigning cores to test buses. We present experimental results that demonstrate the effectiveness of the proposed method.

We propose a technique to integrate core selection in the SOC (system-on-chip) test solution design-flow. It can, in contrast to previous approaches, be used in the early design-space exploration phase (the core selection process) to evaluate the impact on the system's final test solution imposed by different design decisions, i.e. the core selection and the cores' test characteristics. The proposed technique includes the interdependent problems: test scheduling, TAM (test access mechanism) design, test set selection and test resource floor-planning, and it minimizes a weighted cost-function based on test time and TAM routing cost while considering test conflicts and test power limitations. An advantage with the technique is the novel three-level power model: system, power-grid, and core. We have implemented and compared the proposed technique, a fast estimation technique and a computational extensive pseudo-exhaustive method, and the results demonstrate that our technique produces high quality solutions at reasonable computational cost.

Test access mechanism (TAM) optimization and test data compression lead to a reduction in test data volume and testing time for SOCs. In this paper, we integrate for the first time both these approaches into a single test methodology. We show, how an integrated test architecture based on TAMs and test data decoders can be designed. The proposed approach offers considerable savings in test resource requirements. Two case studies using the integrated test architecture are presented. Experimental results on rest data volume reduction, savings in test application time and the low test pin overheads for a benchmark SOC demonstrate the effectiveness of this approach.

The increased usages of multi-core systems diminish per-core complexity and also demand several parallel design and test technologies. This paper introduces a novel test access mechanism (TAM) for parallel testing of multiple identical cores. Instead of typical test response data from the cores, the test output data used in this paper are the majority values extracted from the typical test response from the cores. All the cores can be tested in parallel and test costs (test time, test pins) are exactly the same as for a single core. The experiment results in this paper show the proposed TAM can test multiple cores with minimal test pins and test time and with negligible hardware overhead.

With the increase of the number of IP cores integrated in SOC, the functions of SOC ar e becoming more complexed. Test time and test cost grow rapidly, therefore it becomes bo ttleneck of SOC test. Test scheduling is one of the efficient approaches to solve the forenamed ques tion. Cross-entropy method, which is ba sed on probability density function, has been used to solve the SOC test scheduling problem. Experimental results on ITC’02 benchmarks show that the proposed method provides better test time results compared to the Linear-Programming. Keywords: System on chip, test scheduling, cross-entropy method 1. INTRODUCTION In order to shorten the time to market, core based system-on-chip (SOC) design has becomed a widely used technique of integrated circuit design. Compared with system-on-board, work frequency of SOC has improved observably because signal transfers delay is avoid. However, the testing of SOC and the reusable cores becomes a bottleneck of the SOC development. The SOC test includes test information exchange mechanism, test wrapper generation, test access mechanism (TAM) design, test controller design, test schedulin g and test integration, etc. Among the SOC test issues, the test scheduling is one of the most important challenges. Many works have forced on core test scheduling to minimize the overall testing time, in [7], the test scheduling is mapped to the linear programming (LP) problem, but the computation time is too long. In this paper, we use a cross-entropy (CE) method, which is based on probability density function, to solve the test scheduling problem. The paper is organized as follows. In section II, the test scheduling problem is briefly described. We formulate the problem of test scheduling using CE method in section III. Experimental results are given in section IV, and section V concludes the paper.

A novel test access mechanism (TAM) architecture with multi test-channel (TC) based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip (SoC) test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC’02 test benchmark.

Testing NoC-based systems mainly relies on reusing the Network-on-Chip architecture as the test access mechanism (TAM). This, however, implies that the core's test wrapper is supplied with full NoC channel width even if there is a mismatch between the two. How to effectively and efficiently make better utilization of the NoC channels for test data transferring is therefore an interesting and challenging problem. In this paper, we propose to combine a new wrapper design with interleaved test scheduling. Compared to [8], the proposed method can achieve better NoC channel utilization for test without manipulating test frequencies, which not only reduces test power, but also saves design effort for the test engineers. Consequently, the testing time of the NoC-based system is considerably reduced with the proposed technique (especially under stringent power constraints), as shown in the experimental results on circuits crafted from ITC02 benchmarks.

Test scheduling is an important task for the test of a system on chip, and it determines the assignment of cores to the test access mechanism such that the overall test time is minimized. A new test scheduling approach based on cultural algorithms for system on chip is presented in this paper. First of all, the optimization model of test scheduling is given, the model uses the information such as the bits width of the test access mechanism and the scale of test sets of cores, the crosstalk fault test sets of core interconnect lines is also discussed. Secondly, a method based on cultural algorithms is proposed to solve the optimization model of test scheduling. The ant colony algorithm is used in the population space, and the conventional genetic algorithm is used in the belief space. The feasible solutions of test scheduling are represented by individuals, a lot of individuals form the populations. The optimal test scheduling scheme is obtained by the evolution of the populations. Experimental results on a lot of benchmark circuits show that the proposed approach in this paper can solve the problem of test scheduling effectively.

We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of test resources (e.g., test access mechanisms (TAM)), we determine the test plan for the application of the tests to the SOC. Test planning in this paper refers to the combined activities of test access architecture partitioning and test scheduling. These activities must be performed in conjunction as the choice of the test access architecture influences the test schedule. We justify the formulation of test scheduling w.r.t. minimum average completion time criterion as compared to minimum makespan. We show that then the problem of scheduling tests on TAMs can be mapped onto a graph theoretic problem which has a polynomial time optimal solution. We have implemented our algorithm as a test planner tool TPLAN. We present the theoretical analysis of our approach in this paper, and compare our results against those published earlier using integer linear programming techniques with encouraging results.

Test scheduling for core-based SoCs is a challenging problem. Test schedules must be crafted with the objectives of minimizing testing time and ATE vector memory requirements, to reduce test cost, under the constraints of total available test access mechanism (TAM) width. Prior research in test scheduling has mainly used search procedures like ILP and rectangle packing to solve this problem, but these approaches are inherently computationally expensive. In this paper we describe a novel algorithm to solve the test scheduling problem using a combination of network flow algorithms, malleable job scheduling and reconfigurable wrapper design. Our approximation algorithm has polynomial time complexity and produces schedules close to the theoretical lower bound. Extensive experimental results using the new ITC'02 SoC benchmarks validate the quality of our solutions.

Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a single chip. Being able to rapidly develop, manufacture, test, debug and verify complex SOCs is crucial for the continued success of the electronics industry. This growth is expected to continue full force at least for the next decade, while making possible the production of multimillion transistor chips. However, to make its production practical and cost effective, the industry road maps identify a number of major hurdles to be overcome. The key hurdle is related to test and diagnosis. This embedded tutorial analyzes these hurdles, relates them to the advancements in semiconductor technology and presents potential solutions to address them. These solutions are meant to ensure that test and diagnosis contribute to the overall growth of the SOC industry and do not slow it down. This embedded tutorial in addition presents the state-of-the-art in system-level integration and addresses the strategies and current industrial practices in the test of system-on-chip. It discusses the requirements for test reuse in hierarchical design, such as embedded test strategies for individual cores, test access mechanisms, optimizing test resource partitioning, and embedded test management and integration at the System-on-Chip level. Processor cores being one of the most common cores embedded in a SOC, issues related to self-testing embedded processor cores are addressed. Future research challenges and opportunities are discussed in enabling testing of future SOCs which use deep submicron technologies.

System on a chip (SOC) based on reusable IP core has been widely used in integrated circuit (IC) design and manufacturing. However SOC efficient test is still the bottle-neck issue. Test scheduling can enhance parallel test to minimize test application time at SOC system level. We present a modified differential evolution (MDE) approach to solve the problems of test scheduling and test access mechanism (TAM) partition for system on chips. A new hybrid mutation mechanism based on the probability estimation operator is introduced in the paper for better handling test scheduling, where the first variation coefficient stays the same but the second variation coefficient changes with iterative times. The different evolutionary strategies are adopted to accelerate effectively convergence without loss in population diversity as far as possible. Different mutation operators and evolutionary strategies are combined to get optimal results. The experimental results on ITC'02 SOC benchmarks are encouraging compared with the improved quantum-inspired evolutionary (IQI), genetic algorithm (GA), the integer linear programming formulation (ILP) and heuristic approaches.

Based on a recent pre-bond TSV probing technique, this paper proposes an iterative greedy procedure to sort the order of test sessions for reducing pre-bond TSV test time. We then combine that session sorting procedure with two existing methods to develop a 3-Step test time Optimization Simulator named "SOS3". SOS3 consists of an ILP (integer linear programming) model for session generation, the greedy procedure for session sorting, and a TSV identification algorithm for early test termination. Experiments are done for various TSV networks and two observations are made. First, session sorting plays an important role within SOS3 as it helps to further reduce pre-bond test time expectation and thus reduces pre-bond TSV test cost. Second, SOS3 as a framework greatly speeds up the pre-bond TSV test.