Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction

본 논문에서는 스캔 체인의 레이아웃 거리를 고려한 효율적인 Test Wrapper 설계 방식을 제안한다. SoC내의 스캔체인들을 태스트하기 위해서는 외부 TAM 라인(line)에 각 스캔체인들을 할당해야 한다. IP 내에 존재하는 스캔체인들은 정상모드에서는 타이밍 위반(Timing Violation)이 발생하지 않도록 레이아웃이 되지만, 테스트 모드에서는 TAM 라인(line)과 연결되는 스캔체인들 간에 부가적인 레이아웃 거리를 갖게 되므로 스캔체인에서 타이밍 위반이 발생될 수 있다. 본 논문에서는 타이밍 위반이 발생하지 않도록 체인간 레이아웃거리를 고려하여 스캔체인을 할당하는 새로운 test wrapper 설계 방식을 제안하였다. We present the efficient test wrapper design methodology considering the layout distance of scan chain. To test the scan chains in SoC, the scan chains must be assigned to external TAM(Test Access Mechanism) lines. The scan chains in IP were placed and routed without any timing violation at normal mode. However, in test mode, the scan chains have the additional layout distance after TAM line assignment, which can cause the timing violation of flip-flops in scan chains. This paper proposes a new test wrapper design considering layout distance of scan chains with timing violation free.

This paper proposes a new parallel test access strategy for multiple identical cores in a network-on-chip (NoC). The proposed test strategy takes advantage of the regular design of NoC to reduce both test area overhead and test time. The proposed NoC reused test access mechanism (TAM) adopted a pipelining structure and a deterministic test data routing algorithm in order to reuse the full bandwidth of links in the NoC. Also, the architecture has complete scalability according to the number of cores and applications for 3D environment are also represented. Experimental results show that the proposed TAM can test multiple cores with the same test time as a single core and negligible hardware overhead.

Previous work on testing NoC-based systems has shown that the integrated network can be efficiently reused as test access mechanism (TAM). These approaches exploit the given infrastructure for data transportation. Beyond that, NoC-architectures for nanoscale systems also have to ensure a reliable communication by additional hardware and/or software measures. For example a cyclic redundancy check (CRC) may be added to protect the end-to-end communication between network resources. This paper presents an approach to reuse the CRC hardware for a compression scheme similar to LFSR-reseeding. The experimental results show that competitive compression ratios can be achieved at low extra cost. This way, core testing in NoC-based systems can benefit from test data compression even for standard cores without integrated decompressors.

According to embedded IP core structure and various DFT strategies, it is difficult to test NoC-based SoC especially for reuse situation. The paper proposes the design of a compatible IEEE 1500 standard core test wrapper, which makes different IP cores homogeneous from the point of test integration. A test response comparator is added to the test wrapper, which is capable of verifying directly whether there is failure in this IP. The comparator not only improves testing efficiency and also supports various test modes. The function and timing simulation of proposed wrapper are accomplished on ISCAS '89 circuits. A 2D Mesh NoC was constructed based on these wrappered IP cores and implemented unicast and multicast testing. The experimental results show that the wrapper can effectively realize embedded IP test access and isolation, and has the good adaptability to support various NoC test strategies.

The increased usages of multi-core systems diminish per-core complexity and also demand several parallel design and test technologies. This paper introduces a novel test access mechanism (TAM) for parallel testing of multiple identical cores. Instead of typical test response data from the cores, the test output data used in this paper are the majority values extracted from the typical test response from the cores. All the cores can be tested in parallel and test costs (test time, test pins) are exactly the same as for a single core. The experiment results in this paper show the proposed TAM can test multiple cores with minimal test pins and test time and with negligible hardware overhead.

With the increase of the number of IP cores integrated in SOC, the functions of SOC ar e becoming more complexed. Test time and test cost grow rapidly, therefore it becomes bo ttleneck of SOC test. Test scheduling is one of the efficient approaches to solve the forenamed ques tion. Cross-entropy method, which is ba sed on probability density function, has been used to solve the SOC test scheduling problem. Experimental results on ITC’02 benchmarks show that the proposed method provides better test time results compared to the Linear-Programming. Keywords: System on chip, test scheduling, cross-entropy method 1. INTRODUCTION In order to shorten the time to market, core based system-on-chip (SOC) design has becomed a widely used technique of integrated circuit design. Compared with system-on-board, work frequency of SOC has improved observably because signal transfers delay is avoid. However, the testing of SOC and the reusable cores becomes a bottleneck of the SOC development. The SOC test includes test information exchange mechanism, test wrapper generation, test access mechanism (TAM) design, test controller design, test schedulin g and test integration, etc. Among the SOC test issues, the test scheduling is one of the most important challenges. Many works have forced on core test scheduling to minimize the overall testing time, in [7], the test scheduling is mapped to the linear programming (LP) problem, but the computation time is too long. In this paper, we use a cross-entropy (CE) method, which is based on probability density function, to solve the test scheduling problem. The paper is organized as follows. In section II, the test scheduling problem is briefly described. We formulate the problem of test scheduling using CE method in section III. Experimental results are given in section IV, and section V concludes the paper.

Nowadays System on Chip (SoC) is expected to perform a large number of applications as per the requirement of customers. Increase in the number of applications leads to an increase in the number of cores inside the SoC. Customers want to use a large number of applications in their product but in a cheap price. In this price competitive market, the manufacturer can not increase the price above a certain range in order to sustain in the market. It is decisive to have a high-quality product with the low price. Testing each core thoroughly can require high amount of time and increases the test economics. Hence it is better to cover significant faults only and test the cores partially. In this paper, we propose a method for incomplete testing of the SoC cores, which recedes Test Power (TP) and Test Data Volume (TDV). Our method persists significant fault coverage and tests most of the significant faults. We also propose a power aware Test access mechanism (TAM) architecture compatible with the reduced test vectors. It provides a trade-off between quality of product and testing parameters (i.e., TP, TDV). Results from experiments exhibit an effective reduction in TDV, TP with a nominal compromise on the quality of testing.

This paper proposes a Numeral-Based Crosstalk Avoidance Coding (NB-CAC) to protect communication channels of Network-on-Chips (NoCs) against crosstalk faults. The NB-CAC scheme produces code words without bit patterns '101' and '010' to eliminate harmful transition patterns from NoC channels. This is done by the use of a new numeral system proposed in the paper. Using the proposed numeral system, the NB-CAC scheme 1) can be utilized in NoC channels with any arbitrary width, and 2) can be implemented with low area, power, and timing overheads. VHDL and SPICE simulations have been carried out for a wide range of channel widths to evaluate delay, area, and power consumption of the NB-CAC codecs. Results of simulations reveal that the NB-CAC scheme completely removes crosstalk faults from NoC channel. In addition, the NB-CAC scheme provides reductions of 17.3% in area and 31.9% in power-delay product with respect to Fibonacci-based coding which has been recently proposed in literature.

Test access is a major problem in testing embedded cores as it directly impacts testing time and hardware cost. Test access mechanism (TAM) is responsible for test data transport and is characterized by its bandwidth capacity. Efficient TAM design is of critical importance in SOC system integration since a test architecture should reduce test cost by minimizing test application time. In this paper, we propose a genetic algorithm to design test access architectures while investigating test bus sizing concurrently with assigning cores to test buses. We present experimental results that demonstrate the effectiveness of the proposed method.

We propose a technique to integrate core selection in the SOC (system-on-chip) test solution design-flow. It can, in contrast to previous approaches, be used in the early design-space exploration phase (the core selection process) to evaluate the impact on the system's final test solution imposed by different design decisions, i.e. the core selection and the cores' test characteristics. The proposed technique includes the interdependent problems: test scheduling, TAM (test access mechanism) design, test set selection and test resource floor-planning, and it minimizes a weighted cost-function based on test time and TAM routing cost while considering test conflicts and test power limitations. An advantage with the technique is the novel three-level power model: system, power-grid, and core. We have implemented and compared the proposed technique, a fast estimation technique and a computational extensive pseudo-exhaustive method, and the results demonstrate that our technique produces high quality solutions at reasonable computational cost.

Test data travels through a System-on-Chip (SOC) from the chip pins to the module-under-test and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented with dedicated wires. However, also existing functional interconnect, such as a bus or Network-on-Chip (NOC), can be reused as TAM. This will reduce the overall design effort and the silicon area. For a given module, its test set, and maximal bandwidth that the functional interconnect can offer between ATE and module-under-test, our approach designs a test wrapper for the module-under-test such that the test length is minimized. Unfortunately, it is unavoidable that with the test data also unused (idle) bits are transported. This paper presents a TAM bandwidth utilization analysis and techniques for idle bits reduction, to minimize the test length. We classify the idle bits into four types which explain the reason for bandwidth under-utilization and pinpoint design improvement opportunities. Experimental results show an average bandwidth utilization of 80%, while the remaining 20% is consumed by the idle bits.

Test access mechanism (TAM) optimization and test data compression lead to a reduction in test data volume and testing time for SOCs. In this paper, we integrate for the first time both these approaches into a single test methodology. We show, how an integrated test architecture based on TAMs and test data decoders can be designed. The proposed approach offers considerable savings in test resource requirements. Two case studies using the integrated test architecture are presented. Experimental results on rest data volume reduction, savings in test application time and the low test pin overheads for a benchmark SOC demonstrate the effectiveness of this approach.

With the increasing complexity and chip scale of SoC, the test problem is becoming more difficult and important. Adding DFT (design for testability) in SoC design period has become the main method for solving the test problem. Based on analyzing some common DFT structures such as Fscan-Bscan, Fscan-Tbus, and the standard for embedded core test (SECT) IEEE P1500, a system-level mixed DFT-TAM (test access mechanism) structure has been presented in this paper. In this structure, different DFT methods are applied in different characteristic IP (intellectual property) cores to pursue the reasonable testing cost, then, a more flexible TAM is built in the system level for achieving every IP core test and testing the connection faults between two IP cores. By some experiments with the programmable video add data (VAD) SoC introduced in this paper, the higher fault coverage and lower test cost could be gotten

During IC manufacturing phase, discriminating between good and faulty chips is not enough. In fact, especially in the first phase of the production of a new device, a complete understanding of the possible failures is quickly required to ramp up production yield. For test engineers, dealing with the manufacturing test of Systems-on-chip (SoCs) means to tackle the extraction of diagnostic data from faulty chips. Another equally important aim of diagnosis, in a later step of a product lifecycle, is to find the real root cause of silicon misbehaviors for field returns. At the core test layer, the adoption of diagnosis-oriented Design-for-Testability structures is almost mandatory and many solutions have been worked out for several types of cores; diagnosis data retrieval often consists in the execution of a set of self-test procedures whose application order and/or customization may depend on the obtained results themselves. This paper details the characteristics of a system-layer test architecture able to manage efficiently SoC self-diagnostic procedures. This architecture is composed of a diagnosis-oriented Test Access Mechanism (TAM) and an Infrastructure-IP owning enough intelligence to automatically manage core diagnostic procedures. Both of them have been designed in compliance with the IEEE 1500 Standard for Embedded Core Test and exploit the characteristics of Self-Test structures inserted for the diagnosis of memory, processor and logic cores. This approach to SoC diagnosis minimizes ATE memory requirements for pattern storage and drastically speeds up the complete execution of diagnostic procedures. Experimental results highlight the convenience of the approach with respect to alternative ATE driven diagnosis procedures, while resorting to negligible area overhead.

In this paper, a test access mechanism named TESTLINE and its test time and power optimization algorithm for SOC test is presented. TESTLINE just needs 5 pins and can provide high-speed parallel test scheme. TESTLINE has a scalable mechanism. Its schematic can be easily configured according to test time and test power. ILP (Integer Linear Programming) is used to find the optimal results. TESTLINE also is a hierarchical structure. It is easy to build a hierarchical test access mechanism.