Traffic characterization for multicasting in NoC

In this survey, we review several approaches for predicting performance of Network-on-Chip (NoC)-based multicore systems, starting from the traffic models to the complex NoC models for latency evaluation. We first review typical traffic models to represent the application workloads in NoC. Specifically, we review Markovian and non-Markovian (e.g., self-similar or long-range memory-dependent) traffic models and discuss their applications on multicore platform design. Then, we review the analytical techniques to predict NoC performance under given input traffic. We investigate analytical models for average as well as maximum delay evaluation. We also review the developments and design challenges of NoC simulators. One interesting research direction in NoC performance evaluation consists of combining simulation and analytical models in order to exploit their advantages together. Toward this end, we discuss several newly proposed approaches that use hardware-based or learning-based techniques. Finally, we summarize several open problems and our perspective to address these challenges.

Two network-on-chip (NoC) designs are examined and compared in this paper. One design applies a bidirectional ring connection scheme, while the other design applies a code-division multiple-access (CDMA) connection scheme. Both of the designs apply globally asynchronous locally synchronous (GALS) scheme in order to deal with the issue of transferring data in a multiple-clock-domain environment of an on-chip system. The two NoC designs are compared with each other by their network structures, data transfer principles, network node structures, and their asynchronous designs. Both the synchronous and the asynchronous designs of the two on-chip networks are realized using a hardware-description language (HDL) in order to make the entire designs suit the commonly used synchronous design tools and flow. The performance estimation and comparison of the two NoC designs which are based on the HDL realizations are addressed. By comparing the two NoC designs, the advantages and disadvantages of applying direct connection and CDMA connection schemes in an on-chip communication network are discussed.

The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC (MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it is foreseen that conventional NoC architectures cannot sustain the performance, power, and reliability requirements demanded by the next generation of manycore architectures. Recently, emerging on-chip communication technologies, like wireless Networks-on-Chip (WiNoCs), have been proposed as candidate solutions for addressing the scalability limitations of conventional multi-hop NoC architectures. In a WiNoC, a subset of network nodes are equipped with a wireless interface which allows them long-range communication in a single hop. Assessing the performance and power figures of NoC and WiNoC architectures requires the availability of simulation tools that are often limited on modeling specific network configurations. This article presents Noxim, an open, configurable, extendible, cycle-accurate NoC simulator developed in SystemC, which allows to analyze the performance and power figures of both conventional wired NoC and emerging WiNoC architectures.

In Many/Multi-core processor architectures, hundreds and thousands of Intellectual Property (IP) cores are integrated to reinforce parallel processing and high performance computing. Integration of IP cores is effectively realized by a scalable communication framework, Network on Chip (NoC). NoC comprises of routers and interconnection links which aid transfer of information between IP cores. It is the router which dominants the performance of NoC. A baseline router incorporates the FIFO (First In First Out) buffers, the routing computation logic, the arbiter and the crossbar switch fabric. In this paper, we propose different techniques of merging arbitration and switching functionalities accomplished in wormhole NoC router. Proposed microarchitectures for merging these functionalities are Merged Arbitration and Switching (MAS) microarchitecture based on multiplexer reorganization, Pipelined Merged Arbitration and Switching (PMAS) microarchitecture based on Pipelining and Wave-pipelined Merged Arbitration and Switching (WMAS) microarchitecture based on Wave-pipelining. Synthesis results show that the MAS microarchitecture outperforms the Merged ARbiter and multipleXer (MARX) microarchitecture in area and power consumption by 21.8% and 39.5% respectively. Simulation results show that the PMAS and WMAS microarchitectures outperform MARX microarchitecture in throughput by 40% and 60% respectively at a marginal cost of area and power consumption. Therefore, the benefits of using MAS microarchitecture in wormhole NoC router is low area and power consumption and PMAS or WMAS microarchitecture is high throughput.

Network on Chip (NoC) concept has evolved as a standard design approach for integrating large number of processing cores within a single die. The performance improvements which occur due to topological optimizations and architectural enhancements of NoCs can be remarkably increased by the adoption of 3D IC fabrication technology. However, conventional 3D NoC architecture designs are significantly affected by router area and power dissipation issues when compared with traditional 2D NoCs. Also, 3D NoC utilizes considerable number of Through Silicon Vias (TSVs) which raises area overhead leading to minimal yield and wafer utilization. In this paper, we propose an asymmetric routing approach in bufferless 3D NoC using interleaved edge routers for enhancing NoC performance. Simulation results show that our proposed M-3D (Modified Three Dimensional) mesh design has better throughput, lower average flit latency and deflection rate compared to state-of-the-art bufferless networks, employing same number of routers.

Nowadays reconfigurable Network-on-Chip (NoC) is common high performance on-chip communication architecture for multi-core System-on-Chips (SoCs). This paper improved overall performance of reconfigurable NoC and throughput by using some extra switches and multiplexers. In the proposed architecture, some routers are replaced with 5-port switches. Simple 5-port switches are used for making a shorter path between communicating nodes. In another words, the proposed method can set up direct links between processing elements (PEs) by bypassing the intermediate routers. Static Random Access Memory (SRAM) cells are used to program switches and multiplexers in order to connect (or disconnect) the partial paths which leads to configuration capability in NoC. In order to evaluate the proposed architecture we compared it with the Reconfigurable Network-on-Chip (RNoC). Applying this technique would decrease the average packet delay about 40%, power consumption about 8% and there would enhance about 15% in the throughput so the overall performance would improve. Because of adding extra switches and multiplexers in each node, the architecture has about 24% area overhead.

In the multi-core era, on-chip communication networks are key to system correctness and performance. To deal with their growing complexity, micro-architectural models capture the intent of architects and provide means for formal analysis. However, the analysis of such micro-architectural models is restricted to non-scalable and/or very specific approaches. We present a novel scalable approach to support the symbolic channel type inference of large micro-architectural models described in the xMAS language proposed by Intel. We define an algorithm that computes all possible messages that can occur in a communication channel, treating their payload symbolically. These results can be used for further analysis such as verifying absence of misrouting, deriving inductive invariants and deadlock detection. We illustrate our approach on a Spidergon network developed at STMicroelectronics.

Summary form only given. The SoC (System on Chip) design demands for novel architectural and circuital solutions to cope with the global wires issue, pushing the on-chip communication as a crucial and precious resource. In the context of the communication centric paradigm and according to a layered based design, it is foreseen that current on-chip shared bus will be, at least partially, replaced by a micronetwork interconnection implementing a flexible packet-based communication (A. Jantsch and H. Tenhunen, "Networks on Chip", Kluwer Academic Publishers, 2003). We state that the availability of an efficient on-chip communication platform is one of the most important enabling factors for the development of efficient and cost effective multi processor SoC in the near and long-term future. This summary presents the low cost, high performance on-chip communication network, called Spidergon, developed by the AST (Advanced System Technology) of STMicroelectronics as the possible evolution of STBus technology.

The transmission delay is an important index of the system performance of NoC (Network on Chip). Although the method of simulation-based can get accurate transmission delay, the simulation requires time consuming and a large number of test vectors. Especially in the study of some algorithms, such as mapping algorithms, buffer allocation algorithm, the simulation method is not applicable. To solve the above problems, the paper uses queuing theory to study the establishment of a NoC delay model. The model considers the limited buffer of routing unit and virtual channel technology for network transmission delay and proposes solving algorithm of the delay model based on reverse deduction method. The simulation shows that this model used to analyze the application-specific data transmission delay has smaller average error (reduced by 8%) and higher evaluation efficiency (increased by more than 30 times), which provide designers an efficient method of performance evaluation. DOI: http://dx.doi.org/10.11591/telkomnika.v11i10.3395

Network-on-Chip (NoC) is a popular communication and interconnection structure for multi or many-core system-on-chip (SoC). It mainly consists of routers, network interfaces and communication links. It typically utilizes virtual channels (VCs) to improve wormhole routing among the SoC cores by enabling multiple packet flits to share NoC communication links. DAMQ (Dynamically Allocation Multi Queues) based VC organization has higher buffer utilization but it also has a few problems. We present a novel NoC router architecture that provides solutions to these problems. It utilizes dynamic VC based buffering and index based arbitration methodologies. Arbitration is a critical operation employed in NoC routers that may results in lower speed, weak fairness, and difficulties in pipelining. Our arbitration techniques used in the presented router architecture overcome these problems. We have simulated and implemented our 2D-mesh NoC router using System-Verilog. The experimental results confirm the efficiency of our proposed NoC router in terms of superior router power and ASIC area as well as its operating speed. Performance metrics for different NoC configurations are determined and evaluated for a variety of traffic patterns.

Over the years, system on chip (SoC) designs have evolved extensively sophisticated in order to fulfil the need of increasing complexity of running applications driven by the advancement of VLSI technology. The next generation multiprocessor system on chip (MPSoC) integrates hundreds of processing elements on a single chip, expected to achieve high performance, low latency, and low-power consumption. Tiled chip multicore processors (TCMP) with network on chip (NoC) have become a foundation for the computation critical embedded and real-time systems. Faster time-to-market restraint and business competition compelled manufacturers to look for the prospects of manufacturing SoCs integrated with various third party intellectual property (3PIP). Usage of 3PIP gave rise to exploit the underlying interconnect while adding some unwanted malicious circuit known as hardware trojan (HT), making NoC vulnerable to get attacked. A tiniest manipulation of any communication attribute by HT can degrade the overall behaviour of the system significantly while impacting NoC performance metrics. In this paper, we present one of such study considering HT malign behaviour of manipulating the output port of each incoming flit from specific ports once genuine route computation takes place and re-directs all to one port causing disruption in tile communication.The proposed HT is intermittent in nature and activates for few cycles. We study the behaviour of proposed confluence attack and analyze its impact over network level. The empirical evaluation exhibits the misbehaviour of the packet communication in terms of wrong usage of VCs and extra hop distance overhead. To validate the proposed work, various performance metrics like buffer utilization, virtual channel utilization, number of flits processed, link utilization, and the like are analyzed. We also show that such HTs are difficult to detect due to marginal increase at malicious port traffic leaving no trace of malicious conduct.

This paper proposes a new parallel test access strategy for multiple identical cores in a network-on-chip (NoC). The proposed test strategy takes advantage of the regular design of NoC to reduce both test area overhead and test time. The proposed NoC reused test access mechanism (TAM) adopted a pipelining structure and a deterministic test data routing algorithm in order to reuse the full bandwidth of links in the NoC. Also, the architecture has complete scalability according to the number of cores and applications for 3D environment are also represented. Experimental results show that the proposed TAM can test multiple cores with the same test time as a single core and negligible hardware overhead.

Simulation environment for link energy estimation in networks-on-chip with virtual channels

Network-on-Chip (NoC) has been proposed as a new solution to deal with the global communication problem of complex System-on-Chip (SoC), which faces huge design challenges. A performance evaluation tool is essential for designers to explore the design space, verify functionality and estimate performance of designs. This paper presents a performance evaluation platform of NoC, which can measure and present performance of NoC designs at transaction-level, register-transfer-level and application-level of abstraction. Based on the hierarchical progressive abstraction approach, the platform has been built using SystemVerilog-based Transaction Level Modeling. This platform enables to generate various traffic patterns and support evaluation of multiple levels of service in NoC. Additionally, it is applicable to networks with arbitrary size, topology and multiple interface protocols. The effectiveness and correctness of this platform are verified by evaluating and analyzing specific NoC instances at the end of the paper.

The Network-on-Chip (NoC) is Network-version of System-on-Chip (SoC) means that on-chip communication through packet based networks. In NOC topology, routing algorithm and switching are main terminology. The routing algorithm is one of the key factors in NoC architecture. The routing algorithm which defines as the path taken by a packet between the source and the destination. The paper proposes a novel algorithm for a Network-on-Chip, which is based on packet switching. Using square mesh techniques used for 16 nodes based NoC design and simulation. The node is equal to row and column. Paper discusses internal architecture of NoC using addressable memory and simulate on XILINX 14.1 ISE MODELSIM. Keywords : Network-on-Chip, Static routing, Parallelism Cite this Article Anurag Shrivastava, Sudhir Kumar Sharma. A reliable routing architecture and algorithm for network-on-chip, Journal of Electronic Design and Technology . 2015; 6(3): 40–48p.