Establishing Performance Evaluation Model with Queuing Theory in NoC

Network on Chips (NoC) have emerged as a reliable communication framework in CMPs and SoCs. Many 2-D NoC architectures have been proposed for efficient on-chip communication. The use of 3D IC technology in NoC promises to improve communication latency and power. Most of the 3D ICs use Through-silicon via (TSVs) as vertical interconnect. In this paper, we explore the design space of 2-layer 3D Butterfly Fat Tree (BFT) variants. Floorplan driven wire and TSV lengths are used to obtained power and performance optimal 3D NoC architectures. We analysed the performance of the output flow control using random and round robin output based deflection routing for 3D BFT variants. TSV based power and delay models were extended to a cycle accurate simulator to estimate accurate power and performance of 3D NoC architecture. We propose a new OP3DBFT (Optimal Power and Performance 3DBFT) architecture with round-robin deflection routing (RROD) as power and performance optimal 2-layer 3D NoC architecture. OP3DBFT has symmetric link lengths and 75% of TSVs count reduced compared to the regular 2-layer 3D BFT topology. Results of our experiments show that the performance improved up to 1.39\(\times \) and 1.3\(\times \) in OP3DBFT with fewer TSV counts compared to the regular 2-layer 3D BFT for uniform and transpose traffic respectively. The OP3DBFT NoC architecture EDP (Energy delay product) was lower by 40% for uniform traffic and 48% for transpose traffic.

The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these methods have to address are the generation and evaluation of network traffic. Traffic generation allows injecting packets in the network according to application constraint specifications such as transmission rate and end-to-end latency. Performance evaluation helps in computing latency and throughput at network channels/interfaces, as well as to identify congestion and hot-spots. This paper reviews related works in traffic generation and performance evaluation for mesh topology NoCs, and proposes general methods for both aspects. Three parameters are used here to define traffic generation: packet spatial distribution, packet injection rate and packet size. Two types of methods to evaluate performance in NoCs are discussed: (i) external evaluation, a common strategy found in related works, where the network is considered as a black box and traffic results are obtained only from the external network interfaces; (ii) internal evaluation, where performance is computed in each network channel. The paper presents the result of experiments conducted in an 8times8 mesh network, varying the routing algorithms and the number of virtual channels. The main contribution of this work is the set of methods for internal NoC evaluation, which help designers to optimize the network under different traffic scenarios

Network on Chip (NoC) is an emerging interconnect solution with reliable and scalable features over the System on Chip (SoC) and helps to overcome the drawbacks of bus-based interconnection in SoC. The multiple cores or other networks have a boundary which is limited to communicate with devices, which are directly connected to it. To communicate with these multiple cores outside the boundary, the NOC requires the gateway functionality. In this manuscript, a cost-effective Network Gateway (NG) model is designed, and also the interconnection of a network gateway with multiple cores are connected to the NoC based system is prototyped on Artix-7 FPGA. The NG mainly consists of Serializer and deserializer for transmitting and receiving the data packets with proper synchronization, temporary register to hold the network data, electronic crossbar switch is connected with multiple cores which are controlled by switch controller. The NG with the Router and different sizes of NoC based system is designed using congestion-free adaptive-XY routing. The implementation results and performance evaluation are analyzed for NG based NoC in terms of average Latency and maximum Throughput for different Packet Injection Ratio (PIR). The proposed Network gateway achieves low latency and high throughput in NoC based systems for different PIR.

NoC (Network on Chip) is an emerging paradigm for design of VLSI/ULSI circuits to overcome communication bottleneck of traditional bus based systems. NoC communication framework consists of regularly placed routers, which are connected to processing cores. NoC performance is determined by latency and throughput for communication requirements. NoC communication traffic modelling plays an important role in design of NoC simulators and/or prototypes. This paper presents a framework for modelling source traffic for multipoint communication from one source to different destinations as is required for multicasting. Such a traffic model captures real-world scenarios such as multicasting, execution of concurrent multiple tasks on a single core (each task requiring communication with different destinations). The model proposes how concurrent traffic streams from a single core to different destinations can be mathematically characterized as a single stream at source end. The model is derived from statistical behaviour of probabilistically demultiplexing of a single traffic stream. In its nascent stage, the method is proposed for a scenario of one source concurrently communicating with two destinations as shall be required for mapping two concurrent tasks to same core or simultaneous broadcast to two destinations.

Hexagonal torus networks are special family of Eisenstein-Jacobi (EJ) networks which have gained popularity as goodcandidates network On-Chip (NoC) for interconnecting Multiprocessor System-on-Chips (MPSoCs). They showed better topological properties compared to the 2D torus networks with the same number of nodes. All-to-all broadcast is a collective communicationalgorithm used frequently in some parallel applications. Recently, an off-chip all-to-all broadcast algorithm has been proposed forhexagonal torus networks assuming half-duplex links and all-ports communication. The proposed all-to-all broadcast algorithm does not achieve the minimum transmission time and requires 24 k extra buffers, where k is the network diameter. We first extend this work by proposing an efficient all-to-all broadcast on hexagonal torus networks under full-duplex links and all-ports communications assumptions which achieves the minimum transmission delay but requires 3 6 k extra buffers per router. In a second stage, we develop a new all-to-all broadcast more suitable for hexagonal torus network on-chip that achieves optimal transmission delay time without requiring any extra buffers per router. By reducing the amount of buffer space, the new all-to-all broadcast reduces the routers cost which is an important issue in NoCs architectures.

Network-on-Chip (NoC) has been proposed as a new solution to deal with the global communication problem of complex System-on-Chip (SoC), which faces huge design challenges. A performance evaluation tool is essential for designers to explore the design space, verify functionality and estimate performance of designs. This paper presents a performance evaluation platform of NoC, which can measure and present performance of NoC designs at transaction-level, register-transfer-level and application-level of abstraction. Based on the hierarchical progressive abstraction approach, the platform has been built using SystemVerilog-based Transaction Level Modeling. This platform enables to generate various traffic patterns and support evaluation of multiple levels of service in NoC. Additionally, it is applicable to networks with arbitrary size, topology and multiple interface protocols. The effectiveness and correctness of this platform are verified by evaluating and analyzing specific NoC instances at the end of the paper.

Network on Chips(NoC) emerged as the reliable communication framework in CMPs and SoCs which enables in increase the number and complexity of cores. Many 2-D NoC architectures have been proposed for efficient on-chip communication. Cycle accurate simulators model the functionality and behavior of NoCs by considering micro-architectural parameters of the underlined components to estimate performance metric. Using 3D IC technology in NoC can lead to improved communication latency and power compared to their 2D counterpart with use of through-silicon via (TSVs) as vertical interconnect. In this paper, we explore the design space of 3D variants of the Mesh and Butterfly Fat Tree(BFT) NoCs using floorplan driven wire and TSV lengths. Analysed the performance of 2D and 3D variants of the Mesh and BFT topologies by injecting uniform traffic pattern. Results of our experiments show that, average network latency of a 4-layer 3D Mesh shows better on-chip communication performance compare to other 3D variants. In 4-layer 3D Mesh, on-chip communication performance is improved up to 2.2× compare to 2D Mesh and 4.5× compare to 4-layer 3D BFT.

In Many/Multi-core processor architectures, hundreds and thousands of Intellectual Property (IP) cores are integrated to reinforce parallel processing and high performance computing. Integration of IP cores is effectively realized by a scalable communication framework, Network on Chip (NoC). NoC comprises of routers and interconnection links which aid transfer of information between IP cores. It is the router which dominants the performance of NoC. A baseline router incorporates the FIFO (First In First Out) buffers, the routing computation logic, the arbiter and the crossbar switch fabric. In this paper, we propose different techniques of merging arbitration and switching functionalities accomplished in wormhole NoC router. Proposed microarchitectures for merging these functionalities are Merged Arbitration and Switching (MAS) microarchitecture based on multiplexer reorganization, Pipelined Merged Arbitration and Switching (PMAS) microarchitecture based on Pipelining and Wave-pipelined Merged Arbitration and Switching (WMAS) microarchitecture based on Wave-pipelining. Synthesis results show that the MAS microarchitecture outperforms the Merged ARbiter and multipleXer (MARX) microarchitecture in area and power consumption by 21.8% and 39.5% respectively. Simulation results show that the PMAS and WMAS microarchitectures outperform MARX microarchitecture in throughput by 40% and 60% respectively at a marginal cost of area and power consumption. Therefore, the benefits of using MAS microarchitecture in wormhole NoC router is low area and power consumption and PMAS or WMAS microarchitecture is high throughput.

Network on Chip (NoC) concept has evolved as a standard design approach for integrating large number of processing cores within a single die. The performance improvements which occur due to topological optimizations and architectural enhancements of NoCs can be remarkably increased by the adoption of 3D IC fabrication technology. However, conventional 3D NoC architecture designs are significantly affected by router area and power dissipation issues when compared with traditional 2D NoCs. Also, 3D NoC utilizes considerable number of Through Silicon Vias (TSVs) which raises area overhead leading to minimal yield and wafer utilization. In this paper, we propose an asymmetric routing approach in bufferless 3D NoC using interleaved edge routers for enhancing NoC performance. Simulation results show that our proposed M-3D (Modified Three Dimensional) mesh design has better throughput, lower average flit latency and deflection rate compared to state-of-the-art bufferless networks, employing same number of routers.

In this survey, we review several approaches for predicting performance of Network-on-Chip (NoC)-based multicore systems, starting from the traffic models to the complex NoC models for latency evaluation. We first review typical traffic models to represent the application workloads in NoC. Specifically, we review Markovian and non-Markovian (e.g., self-similar or long-range memory-dependent) traffic models and discuss their applications on multicore platform design. Then, we review the analytical techniques to predict NoC performance under given input traffic. We investigate analytical models for average as well as maximum delay evaluation. We also review the developments and design challenges of NoC simulators. One interesting research direction in NoC performance evaluation consists of combining simulation and analytical models in order to exploit their advantages together. Toward this end, we discuss several newly proposed approaches that use hardware-based or learning-based techniques. Finally, we summarize several open problems and our perspective to address these challenges.

With complexities of systems-on-chips (SoCs) rising almost daily, the system designers have been searching for new design methodology that can handle given complexities with decreased times-to-market. The obvious solution that comes to mind is increasing the level of abstraction. However the system designers also care about the system architectures, HW/SW performance, and communication protocols. Furthermore, the transaction-level model (TLM) can satisfy the requests on complex design with relative high simulation speed and well performance evaluation. In this paper, we implement a TLM-based network-on-chip (NoC) platform and share-bus system architecture with SystemC. We also implement the H.263 encoder as the system application, and apply a design methodology at electronic-system level (ESL) to make design modeling, design space exploration and performance evaluation. Out platform is able to evaluate performance in relatively short time, obtain important information and complete the design more instinctively. In addition, we compare and contrast the NoC and share-bus system architectures in terms of evaluation performance. In experimental result, the performance bottleneck in communication congestion is solved well by using the NoC instead of using the share-bus design.

Network-on-chip (NoC) is being proposed as a scalable and reusable communication platform for future embedded systems. The performance of NoC largely depends on the underlying deadlock-free and efficient routing algorithm. When the adaptive routing returns a set of acceptable output channels, then a selection strategy is used to select the output channel, therefore the selection strategy affects the efficiency of adaptive routing. In this paper a novel selection strategy for avoiding congested areas using a fuzzy-based routing decision is proposed that can be used with any adaptive routing algorithm. The objective of the proposed selection strategy is to choose a channel that has more free slots input buffer and lower power consumption. The routing path is established by minimizing a cost which is calculated by fuzzy controller and considers the power consumption and free slots input buffer of cores. Performance evaluation is carried out by using a flit-accurate simulator under different traffic scenarios. Result experiments show that the proposed selection strategy applied to Odd-Even routing algorithm can effectively improves average delay and power consumption to meet power balance requirement and avoid hotspot with low hardware overhead.

The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC (MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it is foreseen that conventional NoC architectures cannot sustain the performance, power, and reliability requirements demanded by the next generation of manycore architectures. Recently, emerging on-chip communication technologies, like wireless Networks-on-Chip (WiNoCs), have been proposed as candidate solutions for addressing the scalability limitations of conventional multi-hop NoC architectures. In a WiNoC, a subset of network nodes are equipped with a wireless interface which allows them long-range communication in a single hop. Assessing the performance and power figures of NoC and WiNoC architectures requires the availability of simulation tools that are often limited on modeling specific network configurations. This article presents Noxim, an open, configurable, extendible, cycle-accurate NoC simulator developed in SystemC, which allows to analyze the performance and power figures of both conventional wired NoC and emerging WiNoC architectures.

Over the years, system on chip (SoC) designs have evolved extensively sophisticated in order to fulfil the need of increasing complexity of running applications driven by the advancement of VLSI technology. The next generation multiprocessor system on chip (MPSoC) integrates hundreds of processing elements on a single chip, expected to achieve high performance, low latency, and low-power consumption. Tiled chip multicore processors (TCMP) with network on chip (NoC) have become a foundation for the computation critical embedded and real-time systems. Faster time-to-market restraint and business competition compelled manufacturers to look for the prospects of manufacturing SoCs integrated with various third party intellectual property (3PIP). Usage of 3PIP gave rise to exploit the underlying interconnect while adding some unwanted malicious circuit known as hardware trojan (HT), making NoC vulnerable to get attacked. A tiniest manipulation of any communication attribute by HT can degrade the overall behaviour of the system significantly while impacting NoC performance metrics. In this paper, we present one of such study considering HT malign behaviour of manipulating the output port of each incoming flit from specific ports once genuine route computation takes place and re-directs all to one port causing disruption in tile communication.The proposed HT is intermittent in nature and activates for few cycles. We study the behaviour of proposed confluence attack and analyze its impact over network level. The empirical evaluation exhibits the misbehaviour of the packet communication in terms of wrong usage of VCs and extra hop distance overhead. To validate the proposed work, various performance metrics like buffer utilization, virtual channel utilization, number of flits processed, link utilization, and the like are analyzed. We also show that such HTs are difficult to detect due to marginal increase at malicious port traffic leaving no trace of malicious conduct.

Multi-processor System-on-Chip (MPSoC) architectures in future will be imple- mented in less than 50 nm technology and include tens to hundreds of process- ing element blocks operating in the multi-GHz range. The on-chip interconnec- tion network will be a key factor in determining the performance and power consumption of these multi-core devices. Packet switched interconnection net- works or Network-on-Chip (NoC) has emerged as an attractive alternative to tra- ditional bus-based architectures for satisfying the communication requirements of these MPSoC architectures. The key challenge in NoC design is to produce a complex, high performance and low energy architecture under tight time to market requirements. The NoC architectures would support the communication demands of hundreds of cores under stringent performance constraints. In addi- tion to the complexity, the NoC designers would also have to contend with the physical challenges of design in nanoscale technologies. The NoC design prob- lem would entail a joint optimization of the system-level floorplan and power consumption of the network. All these factors coupled with the requirement for short turn around times raises the need for an intellectual property (IP) re-use methodology that is well supported with design and optimization techniques, and performance evaluation models. This chapter introduces the concept of NoC and presents the various elements of the IP-based system-level methodology required for its design.