An Electronic System Level Design and Performance Evaluation for Multimedia Applications

This paper proposes a software based parallel CRC (Cyclic Redundancy Check) algorithm called ' <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N-byte RCC (Repetition of Computation and Combination</i> )''. This algorithm is the iterative process of message computation by the 'slicing-by-4' and combination through the ' <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">zero block lookup tables</i> '. This algorithm can parallelize the CRC calculation with any number of processors. In order to verify the performance of our algorithm, we employ two different communication architectures; the single bus architecture and the 1-star topology NoC (Network on Chip) architecture. With respect to those architectures, we explore our parallel algorithm by using TLM (Transaction Level Model). From the simulation results, we present that the proposed parallel CRC algorithm with BUS and NoC architectures reduces the processing time by 28 percent and 38 percent, respectively, compared to the 'slicing-by-8' which is the fastest algorithms among other software based algorithms. Furthermore, the 1-star NoC architecture of the parallel CRC shows higher performance than the single bus architecture regardless of the number of processors.

A regression-based design space exploration methodology is proposed that models the impacts of the memory hierarchy and the network-on-chip (NoC) on the overall chip multiprocessor (CMP) performance. Designers cannot explore all possible designs for a NoC without considering interactions with the rest of the uncore, in particular the cache configuration and memory hierarchy which determine the amount and pattern of the traffic on the NoC. The proposed regression model is able to capture the salient design points of the uncore for a comprehensive design space exploration by designing memory and NoC-specific regression models and leveraging recent advances in uncore simulation. To show the utility of our methodology, Uncore RPD, two case studies are presented: i) analyzing and refining regression models for an 8-core CMP and ii) performing a rapid design space exploration to find best performing designs of a NoC-based CMP given area-constraints for CMPs of up to 64 cores. Through these case studies, it is shown that i) simultaneous consideration of the memory and NoC parameters in the NoC design space exploration can refine uncore-based regression models, ii) sampling techniques must consider the dynamic design space of the uncore, and iii) overall, the proposed regression models reduce the amount of simulations required to characterize the NoC design space by up to four orders of magnitude.

Network on Chip (NoC) is an emerging interconnect solution with reliable and scalable features over the System on Chip (SoC) and helps to overcome the drawbacks of bus-based interconnection in SoC. The multiple cores or other networks have a boundary which is limited to communicate with devices, which are directly connected to it. To communicate with these multiple cores outside the boundary, the NOC requires the gateway functionality. In this manuscript, a cost-effective Network Gateway (NG) model is designed, and also the interconnection of a network gateway with multiple cores are connected to the NoC based system is prototyped on Artix-7 FPGA. The NG mainly consists of Serializer and deserializer for transmitting and receiving the data packets with proper synchronization, temporary register to hold the network data, electronic crossbar switch is connected with multiple cores which are controlled by switch controller. The NG with the Router and different sizes of NoC based system is designed using congestion-free adaptive-XY routing. The implementation results and performance evaluation are analyzed for NG based NoC in terms of average Latency and maximum Throughput for different Packet Injection Ratio (PIR). The proposed Network gateway achieves low latency and high throughput in NoC based systems for different PIR.

The rapidly increasing complexities of hardware designs are forcing design methodologies and tools to move to the Electronic System Level (ESL), a higher abstraction level with better productivity than the state-of-the-art Register Transfer Level (RTL). Behavioral synthesis, which automatically synthesizes ESL behavioral specifications to RTL implementations, plays a central role in this transition. However, since behavioral synthesis is a complex and error-prone translation process, the lack of designers' confidence in its correctness becomes a major barrier to its wide adoption. Therefore, techniques for establishing equivalence between an ESL specification and its synthesized RTL implementation are critical to bring behavioral synthesis into practice. The major research challenge to equivalence checking for behavioral synthesis is the significant semantic gap between ESL and RTL. The semantics of ESL involve untimed, sequential execution; however, the semantics of RTL involve timed, concurrent execution. We propose a sequential equivalence checking (SEC) framework for certifying a behavioral synthesis flow, which exploits information on successive intermediate design representations produced by the synthesis flow to bridge the semantic gap. In particular, the intermediate design representation after scheduling and pipelining transformations permits effective correspondence of internal operations between this design representation and the synthesized RTL implementation, enabling scalable, compositional equivalence checking. Certifications of loop and function pipelining transformations are possible by a combination of theorem proving and SEC through exploiting pipeline generation information from the synthesis flow (e.g., the iteration interval of a generated pipeline). The complexity brought by bubbles in function pipelines is creatively reduced by symbolically encoding all possible bubble insertions in one pipelined design representation. The result of this dissertation is a robust, practical, and scalable framework for certifying RTL designs synthesized from ESL specifications. We have validated the robustness, practicality, and scalability of our approach on industrial-scale ESL designs that result in tens of thousands of lines of RTL implementations.

The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these methods have to address are the generation and evaluation of network traffic. Traffic generation allows injecting packets in the network according to application constraint specifications such as transmission rate and end-to-end latency. Performance evaluation helps in computing latency and throughput at network channels/interfaces, as well as to identify congestion and hot-spots. This paper reviews related works in traffic generation and performance evaluation for mesh topology NoCs, and proposes general methods for both aspects. Three parameters are used here to define traffic generation: packet spatial distribution, packet injection rate and packet size. Two types of methods to evaluate performance in NoCs are discussed: (i) external evaluation, a common strategy found in related works, where the network is considered as a black box and traffic results are obtained only from the external network interfaces; (ii) internal evaluation, where performance is computed in each network channel. The paper presents the result of experiments conducted in an 8times8 mesh network, varying the routing algorithms and the number of virtual channels. The main contribution of this work is the set of methods for internal NoC evaluation, which help designers to optimize the network under different traffic scenarios

NoC designs can be accepted to provision general communications between multiple IPs above multi-processor schemes on chip. In this effort we demonstrate the forming and imitation based exploration of some current architectures intended for Network on Chip (NoC). Specifically in this paper focus on the time synchronization based network, it hasthe Routing Integrated Time Synchronization protocol (RITS) that integrates post-facto time sync into a routing service also its achieved high result for QoS improvement in network. RITS, as well as reactive techniques in general, is superior to many proactive time sync protocols with respect to communication overhead. The best effort (BF) analysis of a representative reactive technique, the Routing Integrated Time Synchronization protocol (RITS) shows that in the general case, the presence of slack time cause RITS to Guaranteed throughput with the size of the network. We have using a shortest path based Traffic aware algorithm to time based data transmission quickly and efficiently on their network. It has more secure and easy to transfer data from one mobile node to another mobile node on the network.

As the communication sub-system that connecting various on-chip components, Network-on-Chip (NoC) has a great influence on the performance of multi-/many-core processors. Because of NoC model contains a large number of parameters, the design space exploration (DSE) for NoC is a critical problem for the architects. Similar to the core design, existing DSE process mainly depends on iteratively time-consuming simulations. To lower the time budget, many previous studies focus on reducing the simulations. However, most of the proposed works based on regression or machine learning techniques, whose accuracy will be significantly affected by the scale of training set. It still needs a lot of simulations to build the training set.

Communication-centric designs such as network-on-chip (NoC) have been shown to have significant potential in overcoming the problems of increased wire delay and delay variations in deep submicron global interconnect. To further enhance performance, the design parameters of the NoC should be chosen based on the application. In this paper, we identify these parameters and investigate their impact on the NoC system performance. For this purpose, we classified NoC applications into three broad categories, based on the traffic pattern in the network, and simulations were performed with different combinations of the network parameters for each application. We present detailed analysis of this comparative study, which could help system designers in making appropriate choices for the different network parameters in designing an NoC for a particular application.

Network-on-Chip (NoC) based multiprocessors have become popular as a scalable alternative to classical bus architectures. The performance evaluation of NoC-based multiprocessors is largely based on simulation. However, precise simulation is extremely slow. Additionally, there are many design parameters that affect the total performance. Therefore, it is practically impossible to use the precise simulation for the design space exploration purposes. To alleviate this problem, prototyping NoC systems and estimating their performances are critically important. In this paper, we present a generalized novel performance model that combined with the simulations for designing NoC-based multiprocessors. We revealed that the performance impact of cache and network latencies are dominant. Moreover, network congestion rarely happens under near appropriate configuration. Thus, the performance model is mainly constructed using the hardware parameters and the statistics that obtained from a simple cache simulation that is separated from the network behavior. The proposed performance model is used not only to obtain fast and accurate performance, but also to guide the NoC-based multiprocessor design space exploration. The accuracy of our approach and its practical use are illustrated through simulation. The results showed that proposed model can estimate performance with only 3.4% error on average and 21% at worst. We also confirmed that our evaluation framework can estimate 360 times faster than the brute force full system simulation.

The demand of high-performance, scalable and energy-efficient on-chip interconnection network are growing in many-core processors. However, the limitations of the metallic interconnect make electronic Network-on-Chip inefficient. Photonic on-chip networks with advanced CMOS-compatible photonic devices, brings a bright future. In this paper, we present a hierarchical butterfly-based photonic Network-on-Chip, with hybrid router, its topology, and the communication protocol. The proposed network leverages the electronic and photonic technology to improve on-chip network performance. HBPNoC uses hierarchical architecture for packet switching in intra-cluster networks and circuit switching in the inter-cluster network. A butterfly-based structure, comprised of 2×2 photonic switching elements, is used for inter-cluster communication. The simulation results show that our proposed network has very good performance with low optical loss.

The development of digital designs today is much more complex than before, as they now impose more severe demands and require greater number of functionalities to be conceived. The current approach, based on the register transfer level (RTL) design methods, can result in extremely long simulation time compounded with time-consuming verification process. Hence, today digital system design begins with modelling at a higher level of design abstraction, that is, the electronic system level (ESL). This paper presents a hardware-software (HW/SW) co-simulation environment based on SystemC for application in the design of system-on-chip (SoC). We discuss the SystemC modelling of the hardware and the software parts of the system, and the interprocess communication module of the co-simulation platform. Its objective is to help designers obtain an appropriate HW/SW partitioning that satisfy specified area-speed design tradeoffs. Besides, an early system verification can also be carried out with a high simulation speed. A case study of a SoC implementing elliptic curve cryptography (ECC) is presented to validate the co-simulation platform in terms of system functionality verification and design space exploration.

The complexity of modern embedded systems, which are increasingly based on heterogeneous multiprocessor system-on-chip (MPSoC) architectures, has led to the emergence of system-level design. To cope with this design complexity, system-level design aims at raising the abstraction level of the design process from the register-transfer level (RTL) to the so-called electronic system level (ESL). However, this opens a large gap between deployed ESL models and RTL implementations of the MPSoC under design, known as the implementation gap. Therefore, in this chapter, we present the Daedalus methodology which the main objective is to bridge this implementation gap for the design of streaming embedded MPSoCs. Daedalus does so by providing an integrated and highly automated environment for application parallelization, system-level design space exploration, and system-level hardware/software synthesis and code generation.

All computing platforms, from mobile to supercomputers, are becoming more and more heterogeneous and massively parallel. While they can provide higher power efficiency and computation throughput, effective and confident use of these systems always requires knowledge about low-level programming. The average time necessary to develop and optimize a design on heterogeneous platforms is higher and higher compared to typical homogeneous systems. Dataflow models of computation (MoC) are quickly becoming the common practice in heterogeneous systems development. In domains such as signal processing and multimedia communication, dataflow MoCs have become accepted as standard. However, the shift from a sequential and architecture-specific MoC to a dataflow MoC still uncovers several programming and development challenges. The Cal Actor Language (CAL) is a recently-specified dataflow and actor-based language capable of concisely expressing complex and general purpose parallel applications. However, design tools supporting this language are generally not adequate to fully exploit its features and expressiveness power. In fact, they generally restrict its MoC in order to reduce the design space exploration (DSE) effort. The objective of this thesis is to provide a DSE methodology where all the features of CAL and dynamic dataflow MoCs can be exploited in a more general and effective manner. This dissertation illustrates a novel profiling, analysis and performance estimation methodology for the DSE of dynamic dataflow programs. The main research contributions of this thesis are: the formalization of a graph-based representation of the program execution called an execution trace graph (ETG); the formalization of a systematic methodology for profiling generic dynamic dataflow programs through their code interpretation; the formalization of a complete DSE methodology for dynamic dataflow programs in order to efficiently identify close-to-optimal design points according to various and tailored performance merit functions. In particular, the following design space optimization problems for dynamic dataflow programs are addressed: the analysis of the hotspots and the algorithmic bottlenecks of a parallel program; the bounding and optimization of the buffer size configuration for complex designs; the dynamic power dissipation minimization of programs implemented in multi-clock domain architecture. Furthermore, theoretical concepts like the design space critical path and the potential speedup of a dataflow application have been defined and revisited, respectively. The thesis also presents a DSE framework developed in order to demonstrate the effectiveness of this design methodology.

Managing a Network-on-Chip (NoC) in an efficient way is a challenging task. To succeed, the operating system (OS) needs to be tuned to the capabilities and the needs of the NoC. Only by creating a tight interaction can we combine the necessary flexibility with the required efficiency. This paper illustrates such an interaction by detailing the management of communication resources in a system containing a packet-switched NoC and a closely integrated OS. Our NoC system is emulated by linking an FPGA to a PDA. We show that, with the right NoC support, the OS is able to optimize communication resource usage. Additionally, the OS is able to diminish or remove the interference between independent applications sharing a common NoC communication resource.

Multiprocessor Systems-on-Chip (MPSoCs) are a promising solution to fulfill the requirements of high performance computing applications, such as image processing or bioinformatics. Many different MPSoC architectures are introduced by industry and academics, such as Intel's Single Cloud Computer (SCC) or IBM's Cell. To achieve a high efficiency on such MPSoCs a high computing performance in the processing elements (PE) is not the only parameter. The bandwidth of the memory and especially the on-chip communication infrastructure are extremely important to achieve the requirements of the applications. Furthermore, for embedded System-on-Chip solutions, flexibility is extremely important for providing a good tradeoff between performance and power consumption. Especially, for general purpose MPSoCs, designed for a wide range of applications with different communication demands, this flexibility is essential for a good energy efficiency. A simple bus or Network-on-Chip (NoC) with fixed bandwidth and communication paradigm is not sufficient in this varying application scenario and its design space. In this paper novel features for the heterogeneous and runtime adaptive Star-Wheels Network-on-Chip are presented. This Network-on-Chip is used within a runtime adaptive MPSoC, which enables to tailor processors and accelerators to the requirements of the applications. For optimizing the Star-Wheels Network-on-Chip and its communication protocol at runtime to the application requirement the following novel features have been added: the combination of the circuit- and the packet-switched communication paradigm and an algorithm-based placement of the processing elements within the NoC. The integration of the novel algorithm into the design methodology and the exploitation of the novel features within the special purpose runtime operating system of a runtime adaptive MPSoC are also introduced.