High-Speed Parallel Architecture for Software-Based CRC

We present a fast cyclic redundancy check (CRC) algorithm that performs CRC computation for any length of message in parallel. For a given message with any length, we first divide the message into blocks, each of which has a fixed size equal to the degree of the generator polynomial. Then we perform CRC computation among the blocks in parallel using Galois field multiplication and accumulation (GFMAC). Theoretically, our fast parallel CRC algorithm can achieve unlimited speedup over the bit-serial algorithm or byte-wise table lookup algorithm at the expense of adding enough GFMAC units. Our algorithm can perform CRC computation for any lengthy message with two to three clock cycles. In practice, we choose to use a configurable processor where a customized instruction is added to perform multiple pairs of GF multiplication and accumulation. For example, a 4-GFMAC implementation can compute a 32-bit CRC in two to three cycles for a 16-byte message. This level of performance is hundreds of times faster than a bit-serial CRC algorithm or tens of times faster than a byte-wise parallel CRC algorithm. The generator polynomial can be chosen to be software programmed or hard-coded. Our algorithm adds only a small number of logical gates to the processor core.

Cyclic Redundancy Check (CRC) leverages to detect the error of digital data throughout generation, transmission, storage or processing. CRCs are widely used for being simple to execute in binary appliances, crafty to mathematical simulation as well as exclusively performance oriented at identifying generic deviation occured due to intrusion in communication channels. Commonly, hardware implementation of Cyclic Redundancy Check (CRC) computations rely on the Linear Feedback Shift Registers (LFSRs). LFSR framework processes bits serially that is one message bit per clock cycle but while considering high-speed data communications, serial implementation speed is significantly inadequate which causes delay. In this research, a hardware architecture is proposed for parallel computation. Its architecture is not polynomial dependent. After testing its functionality using ModelSim, it is implemented in Altera DE1 FPGA (Field Programmable Gate Array) board and analyzed using Quartus II, TimeQuest Timing Analyzer and Power Play Power Analyzer tools. It is found that the designed took 2771 LEs (Logical Elements), it has 102 pins and consumed 120.68 mW power. Functionality test and FPGA implementation showed that CRC was computed in single clock pulse of frequency of 23.71 MHz and its throughput is 1.656 Gbps. It can be configured for a different polynomial at any time externally. The focus of the research is to represent an efficient, better throughput along with compact systematic interpretation for parallel CRC hardware which will alleviate the flaws including the challenges of the existing CRC checker which will be prominent for next generation high speed communication.

NoC (Network on Chip) architecture exploration is an up to date problem with today's multimedia applications and platforms. The presented methodology gives a solution to easily evaluate timing and resource performances tuning several architectural parameters, in order to find the appropriate NoC architecture with a unique emulation platform. In this paper, a design flow that generates NoC-based emulation platforms on FPGA is presented. From specified traffic scenarios, our tool automatically inserts appropriate IP blocks (emulation blocks and routing algorithm) and generates an RTL NoC model with specific and tunable components that is synthesized on FPGA.

The effectiveness of Network on Chip (NoC) is highly dependent on how well the real-time tasks are mapped on NoC communication infrastructure. In this paper an efficient dynamic scheduling algorithm is proposed and implemented on standard Mesh topology as well as on similar recently proposed LECΔ topology. The performance of proposed algorithm is evaluated in terms of Load Imbalance Factor (LIF), makespan, communication cost and system throughput. The results are evaluated with different task distribution profile using Java-based simulator. The behavior of load distribution is estimated and compared with different performance metrices on two considered topologies. The simulation results show an improvement of 32.57% in LIF at lesser execution time. When comparing the performance of two networks in terms of makespan, the results show a reduction of 43.7% in case of 4 x 4 LECΔ topology as compared to 4 x 4 Mesh topology. The comparative study in terms of LIF, makespan and system throughput is carried out by implementing other existing techniques on both the considered NoC architectures which shows that the proposed approach is an optimized solution for task mapping at considerable reduced cost on considered NoC architectures. The analysis of simulation results shows that the proposed approach may be considered a better choice and implemented on similar NoC architectures as well as other than mesh-based topologies.

The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC (MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it is foreseen that conventional NoC architectures cannot sustain the performance, power, and reliability requirements demanded by the next generation of manycore architectures. Recently, emerging on-chip communication technologies, like wireless Networks-on-Chip (WiNoCs), have been proposed as candidate solutions for addressing the scalability limitations of conventional multi-hop NoC architectures. In a WiNoC, a subset of network nodes are equipped with a wireless interface which allows them long-range communication in a single hop. Assessing the performance and power figures of NoC and WiNoC architectures requires the availability of simulation tools that are often limited on modeling specific network configurations. This article presents Noxim, an open, configurable, extendible, cycle-accurate NoC simulator developed in SystemC, which allows to analyze the performance and power figures of both conventional wired NoC and emerging WiNoC architectures.

Network on Chip (NoC) architectures offer better scalability and performance compared to traditional bus-based interconnects, however low-power consumption in NoC architectures is an important concern that cannot be ignored as high power consumption can lead to increased operating costs, reduced battery life, and thermal management issues. In this work, two well-known NoC architectures such as 3×3 CLICHÉ and 3×3 TORUS architecture have been designed to achieve high performance with minimum power dissipation. The experimental work for designed architectures has been divided into two major parts for analysis. Firstly, the design has been simulated or tested using random input patterns that have been generated with different signal probabilities through the test bench. And secondly, the power of two NoC architectures has been estimated through the physical models, and comparison is done with a simulated tool. For an entire NoC, the total average power is extracted by the simple addition of dynamic and static power. In experimental results, the comparison shows that the total power consumed by the CLICHE architecture is low as compared to TORUS using fix number of Intellectual Property (IP) cores in the network. Also, the average maximum error is estimated to be 18.7 % for power estimation. This highlights the importance of verifying power consumption estimates through physical measurements and testing to ensure the accuracy of the results.

Network on chip (NoC) is a design space covered by the manifold combinations of network topology options, routing algorithms, switch architectures, fault tolerant mechanisms and so on. In NoC structures, switches and links are important components on network layers and the effect of faults on links and switches in NoC leads to disturbance in internal communication and low reliability. The performance reduction of many-core NoC architectures depend strongly on the number of faulty switches. This bottleneck motivates us to propose a fault tolerant switch in which the ring roads help the switch to tolerate the faulty ports and also faulty cores. In the proposed scheme, switch ports are connected via redundant ring roads and so the connection with adjacent nodes is not limited to one port. Moreover, if the switch core is defected, the node stays active and cooperates in packet forwarding process. The main advantages of the proposed scheme are tolerating the permanent faults on core and ports of a switch and handling the input traffic of a faulty switch by preventing the congestion around the faulty region. The simulation results verify the robustness of the proposed intelligent switch against various kinds of permanent faults in NoC architectures.

A network on Chip (NoC) is the interconnection platform that answers the requirements of modern on-Chip design. In this paper we describe an open source FPGA based NoC architecture with low area overhead, high throughput and low latency compared to other published works. The architecture has been optimized for Xilinx FPGAs and the NoC is capable of operating at a frequency of 305.573 MHz in a Virtex-5 xc5vlx110t-3-ff1136 FPGA. We have also developed a bridge so that generic Wishbone bus compatible IP blocks can be connected to the NoC.

Network on-Chip (NoC) is a novel technology which is used to make the interconnections between the components available in the System on Chip (SoC) design. This technology of NoC is defined and used in two varied forms as buffered and bufferless NoC. Bufferless NoC, a predominant type of network on chip, is used to reduce the cost efficiently by removing input buffers of the router. However, it is evident that this performance gets jammed at high loads because of the increase in the network contentions and deflection of packets in huge amount. To reduce the amount of deflection and to buttress the flow, Clumsy Flow Control (CFC) is used in the bufferless NoC. In this paper, a novel proposal has been propounded into the pipelining mechanism keeping in mind the flawless flow control needed for the bufferless NoC to decrease the impact of deflection routing and to increase the throughput with high injection rate. Employing the pipelining technique into the existing flow control increases the frequency which in turn, is responsible for high throughput. Implementation of the aforementioned pipelining mechanism is done in two stages in the bufferless NoC which helps to increase the throughput as well as the injection rate. Finally, the application with its pipelined implementation, as proposed, will be mapped onto the NoC architecture by using the CFC.

This paper presents an efficient method for Regular Expression Matching (REM) by reusing Intellectual Property (IP) cores in a new architecture of Network on Chip (NoC). The method is to design a reusable IP core which consists of many engine cells for REM and to implement each engine cell on a Field Programmable Gate Array (FPGA) as a prototype. To make Finite State Machine (FSM) simpler, a new approach for partitioning a regular expression into several smaller parts is proposed. Each part of a regular expression was matched by an engine cell during matching, and each engine cell communicates with others by routers on a NoC topology. The proposed NoC architecture is a general-purpose design which is suitable for different rule libraries in deep packet inspection (DPI). It can deal with the problem that character self-deplete made the correct regular expression matching missing. A way to use both logic cell and RAM available on FPGA devices is described, and it can make it easier to change the rule library of regular expressions in the RAM. The implementation of the NoC architecture by employing application-specific integrated circuits (ASIC) is finally discussed.

Multi and many-core SoCs (System-on-Chip) are the key solutions to cater for extraordinary demands of high-performance embedded and other applications. It has become more critical with the limits on sub-nanometer technologies for chips that cannot be shrunk further. Network on Chip (NoC) is a scalable interconnection structure that can provide efficient solutions for on-chip interconnection problems of many-core SoCs such as re-configurability for application specific applications. Most of the existing reconfigurable NoCs improve performance of SoC in exchange of larger chip area and higher power. We present a new reconfigurable NoC having improved performance and power for variety of SoC applications. The synthesis and simulation results for our approach show higher performance by comparing our NoC architecture with the past on-chip interconnection structures.

The Network on chip (NOC) architectures provide routing mechanism for various IP blocks in a system on chip (SOC). The existing schemes are based on the techniques are used in networking protocols similar to the conventional Ethernet communication. Such schemes suffer from data overheads and high complexity protocols. A technique based on Direct Sequence Spread Spectrum (DSSS) is proposed with scalable architecture for meeting NOC requirements. High level architecture for data transmission and addressing scheme is designed and simulated in VHDL. The complete scheme is prototyped on Spartan 3E FPGA. The results demonstrate the suitability of the proposed scheme for medium scale SOC applications.

With complexities of systems-on-chips (SoCs) rising almost daily, the system designers have been searching for new design methodology that can handle given complexities with decreased times-to-market. The obvious solution that comes to mind is increasing the level of abstraction. However the system designers also care about the system architectures, HW/SW performance, and communication protocols. Furthermore, the transaction-level model (TLM) can satisfy the requests on complex design with relative high simulation speed and well performance evaluation. In this paper, we implement a TLM-based network-on-chip (NoC) platform and share-bus system architecture with SystemC. We also implement the H.263 encoder as the system application, and apply a design methodology at electronic-system level (ESL) to make design modeling, design space exploration and performance evaluation. Out platform is able to evaluate performance in relatively short time, obtain important information and complete the design more instinctively. In addition, we compare and contrast the NoC and share-bus system architectures in terms of evaluation performance. In experimental result, the performance bottleneck in communication congestion is solved well by using the NoC instead of using the share-bus design.

This paper proposes and evaluates the performance of an all-to-all broadcasting algorithm for a 2D torus Network on Chip (NoC). The proposed algorithm uses special spanning trees called NEWS spanning trees. These trees are link conflict free which implies that the communication steps of the all-to-all algorithm are contention free. The proposed all-to-all broadcasting algorithm is optimal in terms of transmission time and does not need any additional buffer memory like in the all-to-all algorithm for the 2D torus (IEEE Trans Comput 50:1029---1032, 2001). Reducing the amount of buffer space is a very important issue in NoC architectures. Our algorithm is therefore a more efficient solution for all-to-all broadcasting in 2D torus NoC multi-core systems compared to previously proposed algorithms.

The Network-on-Chip (NoC) is Network-version of System-on-Chip (SoC) means that on-chip communication through packet based networks. In NOC topology, routing algorithm and switching are main terminology. The routing algorithm is one of the key factors in NoC architecture. The routing algorithm which defines as the path taken by a packet between the source and the destination. The paper proposes a novel algorithm for a Network-on-Chip, which is based on packet switching. Using square mesh techniques used for 16 nodes based NoC design and simulation. The node is equal to row and column. Paper discusses internal architecture of NoC using addressable memory and simulate on XILINX 14.1 ISE MODELSIM. Keywords : Network-on-Chip, Static routing, Parallelism Cite this Article Anurag Shrivastava, Sudhir Kumar Sharma. A reliable routing architecture and algorithm for network-on-chip, Journal of Electronic Design and Technology . 2015; 6(3): 40–48p.