Design, Implementation, and Power Analysis for Network-on-Chip Architectures

This paper presents an efficient method for Regular Expression Matching (REM) by reusing Intellectual Property (IP) cores in a new architecture of Network on Chip (NoC). The method is to design a reusable IP core which consists of many engine cells for REM and to implement each engine cell on a Field Programmable Gate Array (FPGA) as a prototype. To make Finite State Machine (FSM) simpler, a new approach for partitioning a regular expression into several smaller parts is proposed. Each part of a regular expression was matched by an engine cell during matching, and each engine cell communicates with others by routers on a NoC topology. The proposed NoC architecture is a general-purpose design which is suitable for different rule libraries in deep packet inspection (DPI). It can deal with the problem that character self-deplete made the correct regular expression matching missing. A way to use both logic cell and RAM available on FPGA devices is described, and it can make it easier to change the rule library of regular expressions in the RAM. The implementation of the NoC architecture by employing application-specific integrated circuits (ASIC) is finally discussed.

NoC (Network on Chip) architecture exploration is an up to date problem with today's multimedia applications and platforms. The presented methodology gives a solution to easily evaluate timing and resource performances tuning several architectural parameters, in order to find the appropriate NoC architecture with a unique emulation platform. In this paper, a design flow that generates NoC-based emulation platforms on FPGA is presented. From specified traffic scenarios, our tool automatically inserts appropriate IP blocks (emulation blocks and routing algorithm) and generates an RTL NoC model with specific and tunable components that is synthesized on FPGA.

This paper proposes a software based parallel CRC (Cyclic Redundancy Check) algorithm called ' <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N-byte RCC (Repetition of Computation and Combination</i> )''. This algorithm is the iterative process of message computation by the 'slicing-by-4' and combination through the ' <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">zero block lookup tables</i> '. This algorithm can parallelize the CRC calculation with any number of processors. In order to verify the performance of our algorithm, we employ two different communication architectures; the single bus architecture and the 1-star topology NoC (Network on Chip) architecture. With respect to those architectures, we explore our parallel algorithm by using TLM (Transaction Level Model). From the simulation results, we present that the proposed parallel CRC algorithm with BUS and NoC architectures reduces the processing time by 28 percent and 38 percent, respectively, compared to the 'slicing-by-8' which is the fastest algorithms among other software based algorithms. Furthermore, the 1-star NoC architecture of the parallel CRC shows higher performance than the single bus architecture regardless of the number of processors.

Network-on-chip (NoC) design provides designers a communication infrastructure to integrate heterogeneous intellectual property (IP) cores. To reuse IPs based on shared buses in the NoC architecture, an interface is needed for the NoC communication protocol. In this paper, we present a wrapper design for low-power error-correcting data delivery in on-chip networks. Our wrapper not only provides an interface for reusing IP cores based on the AMBA bus, but also lowers down power dissipation and improves robustness of data transmission. We have implemented this IP wrapper using cell-based design with UMC 0.18 mum technology. It shows that the wrapper design is feasible and efficient.

In Many/Multi-core processor architectures, hundreds and thousands of Intellectual Property (IP) cores are integrated to reinforce parallel processing and high performance computing. Integration of IP cores is effectively realized by a scalable communication framework, Network on Chip (NoC). NoC comprises of routers and interconnection links which aid transfer of information between IP cores. It is the router which dominants the performance of NoC. A baseline router incorporates the FIFO (First In First Out) buffers, the routing computation logic, the arbiter and the crossbar switch fabric. In this paper, we propose different techniques of merging arbitration and switching functionalities accomplished in wormhole NoC router. Proposed microarchitectures for merging these functionalities are Merged Arbitration and Switching (MAS) microarchitecture based on multiplexer reorganization, Pipelined Merged Arbitration and Switching (PMAS) microarchitecture based on Pipelining and Wave-pipelined Merged Arbitration and Switching (WMAS) microarchitecture based on Wave-pipelining. Synthesis results show that the MAS microarchitecture outperforms the Merged ARbiter and multipleXer (MARX) microarchitecture in area and power consumption by 21.8% and 39.5% respectively. Simulation results show that the PMAS and WMAS microarchitectures outperform MARX microarchitecture in throughput by 40% and 60% respectively at a marginal cost of area and power consumption. Therefore, the benefits of using MAS microarchitecture in wormhole NoC router is low area and power consumption and PMAS or WMAS microarchitecture is high throughput.

The effectiveness of Network on Chip (NoC) is highly dependent on how well the real-time tasks are mapped on NoC communication infrastructure. In this paper an efficient dynamic scheduling algorithm is proposed and implemented on standard Mesh topology as well as on similar recently proposed LECΔ topology. The performance of proposed algorithm is evaluated in terms of Load Imbalance Factor (LIF), makespan, communication cost and system throughput. The results are evaluated with different task distribution profile using Java-based simulator. The behavior of load distribution is estimated and compared with different performance metrices on two considered topologies. The simulation results show an improvement of 32.57% in LIF at lesser execution time. When comparing the performance of two networks in terms of makespan, the results show a reduction of 43.7% in case of 4 x 4 LECΔ topology as compared to 4 x 4 Mesh topology. The comparative study in terms of LIF, makespan and system throughput is carried out by implementing other existing techniques on both the considered NoC architectures which shows that the proposed approach is an optimized solution for task mapping at considerable reduced cost on considered NoC architectures. The analysis of simulation results shows that the proposed approach may be considered a better choice and implemented on similar NoC architectures as well as other than mesh-based topologies.

The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC (MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it is foreseen that conventional NoC architectures cannot sustain the performance, power, and reliability requirements demanded by the next generation of manycore architectures. Recently, emerging on-chip communication technologies, like wireless Networks-on-Chip (WiNoCs), have been proposed as candidate solutions for addressing the scalability limitations of conventional multi-hop NoC architectures. In a WiNoC, a subset of network nodes are equipped with a wireless interface which allows them long-range communication in a single hop. Assessing the performance and power figures of NoC and WiNoC architectures requires the availability of simulation tools that are often limited on modeling specific network configurations. This article presents Noxim, an open, configurable, extendible, cycle-accurate NoC simulator developed in SystemC, which allows to analyze the performance and power figures of both conventional wired NoC and emerging WiNoC architectures.

Network on chip (NoC) is a design space covered by the manifold combinations of network topology options, routing algorithms, switch architectures, fault tolerant mechanisms and so on. In NoC structures, switches and links are important components on network layers and the effect of faults on links and switches in NoC leads to disturbance in internal communication and low reliability. The performance reduction of many-core NoC architectures depend strongly on the number of faulty switches. This bottleneck motivates us to propose a fault tolerant switch in which the ring roads help the switch to tolerate the faulty ports and also faulty cores. In the proposed scheme, switch ports are connected via redundant ring roads and so the connection with adjacent nodes is not limited to one port. Moreover, if the switch core is defected, the node stays active and cooperates in packet forwarding process. The main advantages of the proposed scheme are tolerating the permanent faults on core and ports of a switch and handling the input traffic of a faulty switch by preventing the congestion around the faulty region. The simulation results verify the robustness of the proposed intelligent switch against various kinds of permanent faults in NoC architectures.

A network on Chip (NoC) is the interconnection platform that answers the requirements of modern on-Chip design. In this paper we describe an open source FPGA based NoC architecture with low area overhead, high throughput and low latency compared to other published works. The architecture has been optimized for Xilinx FPGAs and the NoC is capable of operating at a frequency of 305.573 MHz in a Virtex-5 xc5vlx110t-3-ff1136 FPGA. We have also developed a bridge so that generic Wishbone bus compatible IP blocks can be connected to the NoC.

Multi-processor System-on-Chip (MPSoC) architectures in future will be imple- mented in less than 50 nm technology and include tens to hundreds of process- ing element blocks operating in the multi-GHz range. The on-chip interconnec- tion network will be a key factor in determining the performance and power consumption of these multi-core devices. Packet switched interconnection net- works or Network-on-Chip (NoC) has emerged as an attractive alternative to tra- ditional bus-based architectures for satisfying the communication requirements of these MPSoC architectures. The key challenge in NoC design is to produce a complex, high performance and low energy architecture under tight time to market requirements. The NoC architectures would support the communication demands of hundreds of cores under stringent performance constraints. In addi- tion to the complexity, the NoC designers would also have to contend with the physical challenges of design in nanoscale technologies. The NoC design prob- lem would entail a joint optimization of the system-level floorplan and power consumption of the network. All these factors coupled with the requirement for short turn around times raises the need for an intellectual property (IP) re-use methodology that is well supported with design and optimization techniques, and performance evaluation models. This chapter introduces the concept of NoC and presents the various elements of the IP-based system-level methodology required for its design.

Network on-Chip (NoC) is a novel technology which is used to make the interconnections between the components available in the System on Chip (SoC) design. This technology of NoC is defined and used in two varied forms as buffered and bufferless NoC. Bufferless NoC, a predominant type of network on chip, is used to reduce the cost efficiently by removing input buffers of the router. However, it is evident that this performance gets jammed at high loads because of the increase in the network contentions and deflection of packets in huge amount. To reduce the amount of deflection and to buttress the flow, Clumsy Flow Control (CFC) is used in the bufferless NoC. In this paper, a novel proposal has been propounded into the pipelining mechanism keeping in mind the flawless flow control needed for the bufferless NoC to decrease the impact of deflection routing and to increase the throughput with high injection rate. Employing the pipelining technique into the existing flow control increases the frequency which in turn, is responsible for high throughput. Implementation of the aforementioned pipelining mechanism is done in two stages in the bufferless NoC which helps to increase the throughput as well as the injection rate. Finally, the application with its pipelined implementation, as proposed, will be mapped onto the NoC architecture by using the CFC.

Modern System-on-Chip (SoC) designs include a variety of Network-on-Chip (NoC) fabrics to implement coordination and communication of integrated hardware intellectual property (IP) blocks. An important class of security vulnerabilities involves a rogue hardware IP interfering with this communication to compromise the integrity of the system. Such interference includes message mutation, misdirection, delivery prevention, or IP masquerading, among others. In this article, we propose a scalable RTL-level SoC validation scheme, SeVNoC, for the systematic detection of security violations in inter-IP communications for SoC designs with NoC fabrics. Given a target security property to be validated, SeVNoC entails extraction of the control-flow graph of the relevant SoC, which is analyzed through a security property-based model comparison, without incurring state-space explosion. Our experiments on full-scale realistic SoC designs with multiple IPs and NoC architecture indicate that SeVNoC detects security violations in NoC communications with near-perfect accuracy, within only a few minutes.

Multi and many-core SoCs (System-on-Chip) are the key solutions to cater for extraordinary demands of high-performance embedded and other applications. It has become more critical with the limits on sub-nanometer technologies for chips that cannot be shrunk further. Network on Chip (NoC) is a scalable interconnection structure that can provide efficient solutions for on-chip interconnection problems of many-core SoCs such as re-configurability for application specific applications. Most of the existing reconfigurable NoCs improve performance of SoC in exchange of larger chip area and higher power. We present a new reconfigurable NoC having improved performance and power for variety of SoC applications. The synthesis and simulation results for our approach show higher performance by comparing our NoC architecture with the past on-chip interconnection structures.

The Network on chip (NOC) architectures provide routing mechanism for various IP blocks in a system on chip (SOC). The existing schemes are based on the techniques are used in networking protocols similar to the conventional Ethernet communication. Such schemes suffer from data overheads and high complexity protocols. A technique based on Direct Sequence Spread Spectrum (DSSS) is proposed with scalable architecture for meeting NOC requirements. High level architecture for data transmission and addressing scheme is designed and simulated in VHDL. The complete scheme is prototyped on Spartan 3E FPGA. The results demonstrate the suitability of the proposed scheme for medium scale SOC applications.

This paper proposes and evaluates the performance of an all-to-all broadcasting algorithm for a 2D torus Network on Chip (NoC). The proposed algorithm uses special spanning trees called NEWS spanning trees. These trees are link conflict free which implies that the communication steps of the all-to-all algorithm are contention free. The proposed all-to-all broadcasting algorithm is optimal in terms of transmission time and does not need any additional buffer memory like in the all-to-all algorithm for the 2D torus (IEEE Trans Comput 50:1029---1032, 2001). Reducing the amount of buffer space is a very important issue in NoC architectures. Our algorithm is therefore a more efficient solution for all-to-all broadcasting in 2D torus NoC multi-core systems compared to previously proposed algorithms.