High Throughput Pipelining NoC using Clumsy Flow Control

Bufferless Network-on-Chip (NoC) emerges as an interesting option for NoC design in recent years, which can save considerable router power and area. However, bufferless NoC only works well under low-to-medium load because it becomes more easily congested as message injection rate increases. In this paper, we propose a novel distributed source-throttling congestion control mechanism that relieves the effect of congestion in bufferless NoC under high load, called Cbufferless. The proposed strategy uses a novel congestion detection and control mechanism, computing average deflection rate of routing flit and distributed throttling message injection. Utilizing the new mechanism, the congestion information can be directly obtained inside node, which allows the mechanism to be fully distributed without requiring any transmission of global congestion information among neighbor routers and within a router. Simulation results show that the proposed mechanism improves system throughput by up to $$\sim $$ ~ 30 and $$\sim $$ ~ 15.5 %, saves energy consumption by up to $$\sim $$ ~ 40 and $$\sim $$ ~ 19 % than that of baseline and injection rate throttling bufferless NoCs, respectively, and keeps lower message latency under congested load when compared.

The Network on chip (NOC) architectures provide routing mechanism for various IP blocks in a system on chip (SOC). The existing schemes are based on the techniques are used in networking protocols similar to the conventional Ethernet communication. Such schemes suffer from data overheads and high complexity protocols. A technique based on Direct Sequence Spread Spectrum (DSSS) is proposed with scalable architecture for meeting NOC requirements. High level architecture for data transmission and addressing scheme is designed and simulated in VHDL. The complete scheme is prototyped on Spartan 3E FPGA. The results demonstrate the suitability of the proposed scheme for medium scale SOC applications.

Network on Chip (NoC) concept has evolved as a standard design approach for integrating large number of processing cores within a single die. The performance improvements which occur due to topological optimizations and architectural enhancements of NoCs can be remarkably increased by the adoption of 3D IC fabrication technology. However, conventional 3D NoC architecture designs are significantly affected by router area and power dissipation issues when compared with traditional 2D NoCs. Also, 3D NoC utilizes considerable number of Through Silicon Vias (TSVs) which raises area overhead leading to minimal yield and wafer utilization. In this paper, we propose an asymmetric routing approach in bufferless 3D NoC using interleaved edge routers for enhancing NoC performance. Simulation results show that our proposed M-3D (Modified Three Dimensional) mesh design has better throughput, lower average flit latency and deflection rate compared to state-of-the-art bufferless networks, employing same number of routers.

NoC (Network on Chip) architecture exploration is an up to date problem with today's multimedia applications and platforms. The presented methodology gives a solution to easily evaluate timing and resource performances tuning several architectural parameters, in order to find the appropriate NoC architecture with a unique emulation platform. In this paper, a design flow that generates NoC-based emulation platforms on FPGA is presented. From specified traffic scenarios, our tool automatically inserts appropriate IP blocks (emulation blocks and routing algorithm) and generates an RTL NoC model with specific and tunable components that is synthesized on FPGA.

A network on Chip (NoC) is the interconnection platform that answers the requirements of modern on-Chip design. In this paper we describe an open source FPGA based NoC architecture with low area overhead, high throughput and low latency compared to other published works. The architecture has been optimized for Xilinx FPGAs and the NoC is capable of operating at a frequency of 305.573 MHz in a Virtex-5 xc5vlx110t-3-ff1136 FPGA. We have also developed a bridge so that generic Wishbone bus compatible IP blocks can be connected to the NoC.

This paper proposes a software based parallel CRC (Cyclic Redundancy Check) algorithm called ' <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N-byte RCC (Repetition of Computation and Combination</i> )''. This algorithm is the iterative process of message computation by the 'slicing-by-4' and combination through the ' <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">zero block lookup tables</i> '. This algorithm can parallelize the CRC calculation with any number of processors. In order to verify the performance of our algorithm, we employ two different communication architectures; the single bus architecture and the 1-star topology NoC (Network on Chip) architecture. With respect to those architectures, we explore our parallel algorithm by using TLM (Transaction Level Model). From the simulation results, we present that the proposed parallel CRC algorithm with BUS and NoC architectures reduces the processing time by 28 percent and 38 percent, respectively, compared to the 'slicing-by-8' which is the fastest algorithms among other software based algorithms. Furthermore, the 1-star NoC architecture of the parallel CRC shows higher performance than the single bus architecture regardless of the number of processors.

QNoC: QoS architecture and design process for network on chip

Network on Chip (NoC) is an emerging interconnect solution with reliable and scalable features over the System on Chip (SoC) and helps to overcome the drawbacks of bus-based interconnection in SoC. The multiple cores or other networks have a boundary which is limited to communicate with devices, which are directly connected to it. To communicate with these multiple cores outside the boundary, the NOC requires the gateway functionality. In this manuscript, a cost-effective Network Gateway (NG) model is designed, and also the interconnection of a network gateway with multiple cores are connected to the NoC based system is prototyped on Artix-7 FPGA. The NG mainly consists of Serializer and deserializer for transmitting and receiving the data packets with proper synchronization, temporary register to hold the network data, electronic crossbar switch is connected with multiple cores which are controlled by switch controller. The NG with the Router and different sizes of NoC based system is designed using congestion-free adaptive-XY routing. The implementation results and performance evaluation are analyzed for NG based NoC in terms of average Latency and maximum Throughput for different Packet Injection Ratio (PIR). The proposed Network gateway achieves low latency and high throughput in NoC based systems for different PIR.

Network on chip (NoC) has been proposed as an attractive alternative to traditional dedicated busses in order to achieve modularity and high performance in the future system-on-chip (SoC) designs. Recently, end to end flow control has gained popularity in the design process of network-on-chip based SoCs. Where flow control is employed, fairness issues need to be considered as well. In fact, one of most difficult aspects of flow control is that of treating all sources fairly when it is necessary to turn traffic away from the network. In this paper, we propose a flow control scheme which admits max-min fairness criterion for all sources. In fact, we formulate weighted max-min fairness criterion for the NoC architecture and present implementation to be used as flow control mechanism.

The Network-on-Chip (NoC) is Network-version of System-on-Chip (SoC) means that on-chip communication through packet based networks. In NOC topology, routing algorithm and switching are main terminology. The routing algorithm is one of the key factors in NoC architecture. The routing algorithm which defines as the path taken by a packet between the source and the destination. The paper proposes a novel algorithm for a Network-on-Chip, which is based on packet switching. Using square mesh techniques used for 16 nodes based NoC design and simulation. The node is equal to row and column. Paper discusses internal architecture of NoC using addressable memory and simulate on XILINX 14.1 ISE MODELSIM. Keywords : Network-on-Chip, Static routing, Parallelism Cite this Article Anurag Shrivastava, Sudhir Kumar Sharma. A reliable routing architecture and algorithm for network-on-chip, Journal of Electronic Design and Technology . 2015; 6(3): 40–48p.

Network on chip (NoC) is a design space covered by the manifold combinations of network topology options, routing algorithms, switch architectures, fault tolerant mechanisms and so on. In NoC structures, switches and links are important components on network layers and the effect of faults on links and switches in NoC leads to disturbance in internal communication and low reliability. The performance reduction of many-core NoC architectures depend strongly on the number of faulty switches. This bottleneck motivates us to propose a fault tolerant switch in which the ring roads help the switch to tolerate the faulty ports and also faulty cores. In the proposed scheme, switch ports are connected via redundant ring roads and so the connection with adjacent nodes is not limited to one port. Moreover, if the switch core is defected, the node stays active and cooperates in packet forwarding process. The main advantages of the proposed scheme are tolerating the permanent faults on core and ports of a switch and handling the input traffic of a faulty switch by preventing the congestion around the faulty region. The simulation results verify the robustness of the proposed intelligent switch against various kinds of permanent faults in NoC architectures.

Network on Chip (NoC) architectures offer better scalability and performance compared to traditional bus-based interconnects, however low-power consumption in NoC architectures is an important concern that cannot be ignored as high power consumption can lead to increased operating costs, reduced battery life, and thermal management issues. In this work, two well-known NoC architectures such as 3×3 CLICHÉ and 3×3 TORUS architecture have been designed to achieve high performance with minimum power dissipation. The experimental work for designed architectures has been divided into two major parts for analysis. Firstly, the design has been simulated or tested using random input patterns that have been generated with different signal probabilities through the test bench. And secondly, the power of two NoC architectures has been estimated through the physical models, and comparison is done with a simulated tool. For an entire NoC, the total average power is extracted by the simple addition of dynamic and static power. In experimental results, the comparison shows that the total power consumed by the CLICHE architecture is low as compared to TORUS using fix number of Intellectual Property (IP) cores in the network. Also, the average maximum error is estimated to be 18.7 % for power estimation. This highlights the importance of verifying power consumption estimates through physical measurements and testing to ensure the accuracy of the results.

Application-Specific Network-on-Chip synthesis with flexible router Placement

The effectiveness of Network on Chip (NoC) is highly dependent on how well the real-time tasks are mapped on NoC communication infrastructure. In this paper an efficient dynamic scheduling algorithm is proposed and implemented on standard Mesh topology as well as on similar recently proposed LECΔ topology. The performance of proposed algorithm is evaluated in terms of Load Imbalance Factor (LIF), makespan, communication cost and system throughput. The results are evaluated with different task distribution profile using Java-based simulator. The behavior of load distribution is estimated and compared with different performance metrices on two considered topologies. The simulation results show an improvement of 32.57% in LIF at lesser execution time. When comparing the performance of two networks in terms of makespan, the results show a reduction of 43.7% in case of 4 x 4 LECΔ topology as compared to 4 x 4 Mesh topology. The comparative study in terms of LIF, makespan and system throughput is carried out by implementing other existing techniques on both the considered NoC architectures which shows that the proposed approach is an optimized solution for task mapping at considerable reduced cost on considered NoC architectures. The analysis of simulation results shows that the proposed approach may be considered a better choice and implemented on similar NoC architectures as well as other than mesh-based topologies.

Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SOCs are application-specific standard products (ASSPs) with limited programmability We describe why TV SOCs must become more flexible, and why companion chips together with networks on chips (NOC) are a crucial enabling technology In particular, networks that span multiple chips will become important in the near future. We demonstrate our ideas by extending a commercially-available SOC for picture improvement in high-end TVs with the /Ethereal NOC. Our first unoptimised results indicate that replacing the original interconnect (consisting of dedicated links and multiplexers for bypasses) by programmable NOC increases the SOC area by 4% and its power dissipation by 12%. The new, flexible SOC allows new tasks to be spliced in at any point in the task graph. Both analytical performance verification and system simulations at RTL VHDL show that the extended SOC meets its functional requirements. Using the /Ethereal design flow the extended architecture was designed, implemented, and verified in 12 person months. To the best of our knowledge, this is the first application of a NOC to a commercial SOC. The quantitative results indicate that even retrofitting a NOC to an existing architecture is beneficial at acceptable cost