Basic Issues

A low power CMOS Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGA) architecture is being presented in this paper. The architecture presented here is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. This architecture employs the fast and low-power SRAM blocks that are based on 10T SRAM cells. These blocks are employed in fast access of the configuration bits by using the shadow SRAM technique. The dynamic reconfiguration delay is being hidden behind the computation delay through the use of shadow SRAM cells. The combined effect of both the SRAM memory cells and the shadow SRAM scheme enables to support in reducing the delay and also to achieve reduced power consumption. Experimental results show reduced delay of about 8.035ns and power consumption of about 0.015W for the 10T SRAM memory cell with an overhead in area, relative to 4T and 6T SRAM cells. Also, the experimental results include the values of delay of about 8.979ns and power consumption of about 0.052W, achieved for the LB of FPGA architecture which employs CMOS SRAMs using the 10T SRAM memory cells in it.

We present a comparative analysis of a fabricated 65nm CMOS static random access memory (SRAM) chip and commercial SRAM chips in terms of security vulnerability. The security vulnerability is defined as the leakage of information due to the data imprinting effect of the SRAM. There are three main features in this evaluation. First, a complete security vulnerability evaluation flow is proposed to stress the SRAM chips for accelerating the negative-biased temperature-instability (NBTI) degradation, i.e. data imprinting effect, and hence to reveal the stored data of image. Second, the evaluation quantifies the percentage of revealed data, i.e. leakage of information for the comparison of tested SRAMs. Third, the image is reconstructed from the revealed data to illustrate the security vulnerabilities of tested SRAMs. We perform the security vulnerability evaluation on the 65nm CMOS SRAM chip and 4 commercial SRAM chips, namely Alliance, Lyontek, Cypress and AMIC under stressing of high voltage and high temperature. From the experimental results, the stored data is significantly revealed in the deep-submicron (≤90nm) CMOS SRAM chips, i.e. fabricated 65nm CMOS (16.1%), Alliance (16.2%) and Lyontek (21%). After reconstructing the images, they can be identified in the 65nm CMOS, Alliance, Lyontek SRAMs, but remain as random states in the Cypress and AMIC SRAMs.

The traditional dynamic random-access memory (DRAM) storage medium can be integrated on chips via modern emerging 3D-stacking technology to architect a DRAM shared cache in multicore systems. Compared with static random-access memory (SRAM), DRAM is larger but slower. In the existing research, a lot of work has been devoted to improving the workload performance using SRAM and stacked DRAM together in shared cache systems, ranging from SRAM structure improvement to optimizing cache tags and data access. However, little attention has been paid to designing a shared cache scheduling scheme for multiprogrammed workloads with different memory footprints in multicore systems. Motivated by this, we propose a hybrid shared cache scheduling scheme that allows a multicore system to utilize SRAM and 3D-stacked DRAM efficiently, thus achieving better workload performance. This scheduling scheme employs (1) a cache monitor, which is used to collect cache statistics; (2) a cache evaluator, which is used to evaluate the cache information during the process of programs being executed; and (3) a cache switcher, which is used to self-adaptively choose SRAM or DRAM shared cache modules. A cache data migration policy is naturally developed to guarantee that the scheduling scheme works correctly. Extensive experiments are conducted to evaluate the workload performance of our proposed scheme. The experimental results showed that our method can improve the multiprogrammed workload performance by up to 25% compared with state-of-the-art methods (including conventional and DRAM cache systems).

SRAM (Static Random Access Memory) is one of the type of memory which holds the data bit without periodic refreshment. Compared with DRAM (Dynamic Random Access Memory) which requires periodic refreshment of data bit stored in it. Unlike Dynamic RAM, Static RAM uses a flip-flop circuit to store each data bit, whereas Dynamic RAM uses a capacitor to store the data bit. But capacitor has tendency of losing charge which requires periodic refreshment. Thus SRAM perform better and have more stability than DRAM especially in idle state. In this work, we analysed the performance of the SRAM cell which are built with different field effect transistors and calculated the Write and Read delays, PDP (Power Delay Product) and Static Noise Margin (SNM) for all types of transistors. SRAM cell which is based on the CNT technology with optimized parameters of CNT density, CNT diameter and CNTFET flat band voltage has the better performance and stability compared with other device technologies. Optimized CNTFET SRAM cell compared with the MOSFET based SRAM the write and read delays are improved by 85.8% and 94.3% respectively. All the simulations have been carried out using HSPICE tool for 32nm technology node.

Several types of CMOS static random access memories (RAMs) have been tested in a cyclotron for susceptibility to single event upsets and latchup such as might occur in earth orbit or interplanetary space. No upsets have been observed for neutron fluences of 10 to the 11th n/sq cm and higher or proton fluences of 10 to the 9th protons/sq cm.

We present a hybrid nanoelectromechanical (NEM)/CMOS static random access memory (SRAM) cell, in which the two pull-down transistors of a conventional CMOS six transistor (6T) SRAM cell are replaced with NEM relays. This SRAM cell utilizes the infinite subthreshold slope and hysteretic properties of NEM relays to dramatically increase the cell stability compared to the conventional CMOS 6T SRAM cells. It also utilizes the zero off-state leakage of NEM relays to significantly decrease static power dissipation. The structure is designed so that the relatively long mechanical delay of the NEM relays does not result in performance degradation. Circuit simulations are performed using a VerilogA model of a NEM relay. Compared to a 65nm CMOS 6T SRAM cell, when 10nm-gap NEM relays (pull-in voltage = 0.8V, pull-out voltage = 0.2V, on resistance = 1ki2) are integrated, hold and read static noise margin (SNM) improve by ~110% and ~250%, respectively. In addition, static power dissipation decreases by ~85%. The write delay decreases by ~60%, while read delay decreases by ~10%. The advantages in SNM and static power dissipation are expected to increase with scaling.

An embedded CMOS static random access memory (SRAM), including the array and a method of accessing cells in the array with improved cell stability for scalability and performance (over 5 GHz) is demonstrated in hardware using 65 nm partially depleted silicon on insulator (PD SOI) technology. The design features shorter bitlines (16 cells/bitline) along with a thin cell layout and programmable domino read operation. Bit lines connected to half selected cells in the array are floated during cell accesses for improved cell stability. In addition, the SRAM is supplied with multiple supplies: one to the cells, wordline drivers, and level shifters, and the other to the bitline and remaining logic to improve stability and lower power

In the era of rapidly advancing technology, the limitations of conventional memory architectures have become a significant bottleneck in meeting the growing demands for data storage and processing. Emerging non-volatile memory technologies are increasingly closing the performance gap between traditional memory and storage solutions, driving innovations in memory cell design. This review provides an overview of conventional memory types, such as static random-access memory (SRAM), dynamic random-access memory (DRAM), and Flash memory, alongside emerging prototype memories like resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), and phase-change memory (PCM). Emerging technology nowadays have a wide range of applications. Resistive random-access memory and spin torque transfer random access memory are the most promising memory for in-memory computing which is advanced beyond conventional von Neumann system, neuromorphic computing mimic human’s brain structure. Internet of things devices and wireless sensor devices make use of the low power consumption memory, and the security is provided by the stochasticity nature of random-access memory which is not desired and is considered as a challenge for memory cell.

In the era of rapidly advancing technology, the limitations of conventional memory architectures have become a significant bottleneck in meeting the growing demands for data storage and processing. Emerging non-volatile memory technologies are increasingly closing the performance gap between traditional memory and storage solutions, driving innovations in memory cell design. This review provides an overview of conventional memory types, such as static random-access memory (SRAM), dynamic randomaccess memory (DRAM), and Flash memory, alongside emerging prototype memories like resistive randomaccess memory (RRAM), magnetoresistive randomaccess memory (MRAM), and phase-change memory (PCM). Emerging technology nowadays have a wide range of applications. Resistive random-access memory and spin torque transfer random access memory are the most promising memory for in-memory computing which is advanced beyond conventional von Neumann system, neuromorphic computing mimic human’s brain structure. Internet of things devices and wireless sensor devices make use of the low power consumption memory, and the security is provided by the stochasticity nature of randomaccess memory which is not desired and is considered as a challenge for memory cell.

The article discusses the search for a novel computing machine. Topics include an idea that every two years the number of transistors on an integrated circuit will double, called Moore's law, research and development (R&D) expenditures of computer chip manufacturers, such as Hewlett-Packard, Intel, and International Business Machines (IBM) Corp., to develop new computing architectures and processor designs, and dynamic random access memory (DRAM) and static RAM (SRAM) systems.

The discovery of giant magnetoresistance (GMR) in magnetic multilayers (Baibich et al., 1988) and of tunnel magnetoresistance (TMR) in metal/insulator junctions (Julliere, 1975) has marked the beginning of spin electronics, which makes use of the electron’s spin as an additional degree of freedom, thus enabling novel phenomena and devices to be imagined. The GMR spin valves (Dieny et al., 1991; Parkin, 1993) have already been integrated in many functional devices like magnetic read heads, angle and position sensors and low-capacity random access memories (RAM). The TMR tunnel junctions are mainly proposed for non-volatile magnetic memories (MRAM) which combine all the advantages of conventional memories such as DRAM (dynamic RAM), SRAM (static RAM) or flash: short access time, non-volatility, insensibility to ionizing radiation, high density, infinite cyclabilty. Major IC manufacturers are now ready to launch the first fully functional prototypes.

Asymmetry in read/write access latencies, which leads to issues of blocking writes and low throughput performance, is a common challenge impeding the integration of emerging nonvolatile memory technologies into high-performance computing systems. Approaches based on multiporting and virtually pipelined architectures, which have been studied in static random access memory (SRAM)/dynamic random access memory (DRAM)/hybrid-SRAM/DRAM memory systems for high throughput performance, provide an attractive means to overcome these challenges through innovations spanning the memory cell to architecture levels. This paper describes a virtually pipelined memory architecture built on a two-port phase change memory (PCM) substrate for high-performance networking applications. The proposed two-port PCM cell significantly reduces the probability of bank conflicts due to blocking writes. We comprehensively evaluate the two-port cell design in terms of programming current, voltage pumping for access transistors, and area overhead. We also propose a two-port PCM bank design to provide the large bandwidth and bank parallelism critical for high-performance networking applications. Furthermore, the virtually pipelined architecture is implemented at the memory controller level, eliminating the extra delay of read requests due to the asymmetrical access latency through separate reservation tables for read and write requests. We analyze the performance of this architecture using queuing theory and statistical information obtained by processing packet traces using PacketBench, and show that the proposed innovations can reduce the expected read (write) delay by 12– $40\times $ (up to 14%) over conventional single-port PCM for 110%–170% additional area.

A Universal Performance Chart for CPU Cooling Devices

The authors describe a 14-ns 1-Mb CMOS SRAM (static random-access memory) with both 1M word*1-b and 256 K word*4-b organizations. The desired organization is selected by forcing the state of an external pin. The fast access time is achieved by the use of a shorter divided-word-line (DWL) structure, a highly sensitive sense amplifier, a gate-controlled data-bus driver, and a dual-level precharging technique. The 0.7- mu m double-aluminum and triple-polysilicon process technology with trench isolation offers a memory cell size of 41.6 mu m/sup 2/ and a chip size of 86.6 mm/sup 2/. The variable bit-organization function reduces the testing time while keeping the measurement accuracy of the access times. >

A strategy for testing for data retention faults in CMOS static random access memories (SRAMs) is proposed. Sensing the voltage at one of the data bus lines with a proper design for testability (DFT) reading circuitry enables the fault-free memory cells from any defective cell(s) to be determined. DFT reading circuitry is also proposed. An analysis of the cost of the proposed approach in terms of area, test time and performance degradation is presented.