HSCS: a hybrid shared cache scheduling scheme for multiprogrammed workloads

SRAM (Static Random Access Memory) is one of the type of memory which holds the data bit without periodic refreshment. Compared with DRAM (Dynamic Random Access Memory) which requires periodic refreshment of data bit stored in it. Unlike Dynamic RAM, Static RAM uses a flip-flop circuit to store each data bit, whereas Dynamic RAM uses a capacitor to store the data bit. But capacitor has tendency of losing charge which requires periodic refreshment. Thus SRAM perform better and have more stability than DRAM especially in idle state. In this work, we analysed the performance of the SRAM cell which are built with different field effect transistors and calculated the Write and Read delays, PDP (Power Delay Product) and Static Noise Margin (SNM) for all types of transistors. SRAM cell which is based on the CNT technology with optimized parameters of CNT density, CNT diameter and CNTFET flat band voltage has the better performance and stability compared with other device technologies. Optimized CNTFET SRAM cell compared with the MOSFET based SRAM the write and read delays are improved by 85.8% and 94.3% respectively. All the simulations have been carried out using HSPICE tool for 32nm technology node.

The discovery of giant magnetoresistance (GMR) in magnetic multilayers (Baibich et al., 1988) and of tunnel magnetoresistance (TMR) in metal/insulator junctions (Julliere, 1975) has marked the beginning of spin electronics, which makes use of the electron’s spin as an additional degree of freedom, thus enabling novel phenomena and devices to be imagined. The GMR spin valves (Dieny et al., 1991; Parkin, 1993) have already been integrated in many functional devices like magnetic read heads, angle and position sensors and low-capacity random access memories (RAM). The TMR tunnel junctions are mainly proposed for non-volatile magnetic memories (MRAM) which combine all the advantages of conventional memories such as DRAM (dynamic RAM), SRAM (static RAM) or flash: short access time, non-volatility, insensibility to ionizing radiation, high density, infinite cyclabilty. Major IC manufacturers are now ready to launch the first fully functional prototypes.

In the era of rapidly advancing technology, the limitations of conventional memory architectures have become a significant bottleneck in meeting the growing demands for data storage and processing. Emerging non-volatile memory technologies are increasingly closing the performance gap between traditional memory and storage solutions, driving innovations in memory cell design. This review provides an overview of conventional memory types, such as static random-access memory (SRAM), dynamic random-access memory (DRAM), and Flash memory, alongside emerging prototype memories like resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), and phase-change memory (PCM). Emerging technology nowadays have a wide range of applications. Resistive random-access memory and spin torque transfer random access memory are the most promising memory for in-memory computing which is advanced beyond conventional von Neumann system, neuromorphic computing mimic human’s brain structure. Internet of things devices and wireless sensor devices make use of the low power consumption memory, and the security is provided by the stochasticity nature of random-access memory which is not desired and is considered as a challenge for memory cell.

In the era of rapidly advancing technology, the limitations of conventional memory architectures have become a significant bottleneck in meeting the growing demands for data storage and processing. Emerging non-volatile memory technologies are increasingly closing the performance gap between traditional memory and storage solutions, driving innovations in memory cell design. This review provides an overview of conventional memory types, such as static random-access memory (SRAM), dynamic randomaccess memory (DRAM), and Flash memory, alongside emerging prototype memories like resistive randomaccess memory (RRAM), magnetoresistive randomaccess memory (MRAM), and phase-change memory (PCM). Emerging technology nowadays have a wide range of applications. Resistive random-access memory and spin torque transfer random access memory are the most promising memory for in-memory computing which is advanced beyond conventional von Neumann system, neuromorphic computing mimic human’s brain structure. Internet of things devices and wireless sensor devices make use of the low power consumption memory, and the security is provided by the stochasticity nature of randomaccess memory which is not desired and is considered as a challenge for memory cell.

The eleven papers in this special section focus on both system- and circuit-level aspects of emerging memory and storage technologies. The overwhelmingly increasing demand for both storage and computation necessitates revisiting the traditional memory subsystems used in processors and storage systems to take advantage of emerging memory technologies. Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) have been ubiquitously used for decades as main memory and as on-chip cache, respectively. Scaling and power issues of these traditional memory technologies have led to significant investment in emerging memory technologies. On the other hand, fundamental limitations of mechanical disk drives have brought great attention to further explore the design space of solid-state drives (SSDs). The promising features of emerging memory technologies such as low power consumption, increased performance, lower susceptibility to particle strikes, and higher bit density have prompted researchers to seek new organizations in the different memory-hierarchy levels, to propose new circuitry and algorithms to improve performance and reduce power consumption, and to develop new schemes to enhance system reliability.

A complete, multi-channel, timing and amplitude measurement IC for use in drift chamber applications is described. By targeting specific resolutions, i.e. 6-bits of resolution for both time and amplitude, area and power can be minimized while achieving the proper level of measurement accuracy. Time is digitized using an TDC comprised of a delay locked loop, latch and encoder. Amplitude (for dE/dx) is digitized using a dual-range FADC for each channel. Eight bits of dynamic range with six bits of accuracy are achieved with the dual-range. Eight complete channels of timing and amplitude information are multiplexed into one DRAM (Dynamic Random Access Memory) trigger latency buffer. Interesting events are subsequently transferred into an SRAM (Static Random Access Memory) readout buffer before the latency time has expired. The design has been optimized to achieve the requisite resolution using the smallest area and lowest power. The circuit has been implemented in an 0.8 /spl mu/m triple metal CMOS process. The measured results indicate that the differential non-linearities of the TDC and the FADC are 200 ps and 10 mV, respectively. The integral non-linearities of the TDC and the FADC are 230 ps and 9 mV, respectively.

Asymmetry in read/write access latencies, which leads to issues of blocking writes and low throughput performance, is a common challenge impeding the integration of emerging nonvolatile memory technologies into high-performance computing systems. Approaches based on multiporting and virtually pipelined architectures, which have been studied in static random access memory (SRAM)/dynamic random access memory (DRAM)/hybrid-SRAM/DRAM memory systems for high throughput performance, provide an attractive means to overcome these challenges through innovations spanning the memory cell to architecture levels. This paper describes a virtually pipelined memory architecture built on a two-port phase change memory (PCM) substrate for high-performance networking applications. The proposed two-port PCM cell significantly reduces the probability of bank conflicts due to blocking writes. We comprehensively evaluate the two-port cell design in terms of programming current, voltage pumping for access transistors, and area overhead. We also propose a two-port PCM bank design to provide the large bandwidth and bank parallelism critical for high-performance networking applications. Furthermore, the virtually pipelined architecture is implemented at the memory controller level, eliminating the extra delay of read requests due to the asymmetrical access latency through separate reservation tables for read and write requests. We analyze the performance of this architecture using queuing theory and statistical information obtained by processing packet traces using PacketBench, and show that the proposed innovations can reduce the expected read (write) delay by 12– $40\times $ (up to 14%) over conventional single-port PCM for 110%–170% additional area.

Various emerging applications such as internet-of-things (IoTs), wearable devices, and neural networks has imposed various challenges on memory design. Conventional memories such as static random access memory (SRAM), dynamic random access memory (DRAM), and flash memory fail to meet many of the requirements in the above applications. Particularly, power is one of the topmost design metrics to be considered. This paper will briefly introduce the recent trend in memory design for various emerging applications.

Accelerator (proton and neutron) measurements of 44 memory device vintages, along with 13 years of avionics processor experience, indicate that Dynamic Random Access Memories (DRAMs), rather than Static Random Access Memories (SRAMs), may become the future memory of choice for protection against atmospheric neutron single event upset.

Representatively, memory has been limitedly used in advances, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Flash Memory. However, nowadays, memory is widely used in smartphones, automobiles, and the Internet of Things (IoT) in everyday electronic devices. Furthermore, there is currently a growing need for high-density memory in terms of size and energy efficiency due to increasing data and computation demands. Non-volatile Memories (NVMs) are promising candidates for achieving fast processing speeds, high data storage density, and energy efficiency because emerging NVMs (STT-MRAM, PCM, ReRAM) offer more of these advantages compared to conventional memory. Among NVMs, ReRAM boasts advantages such as non-volatility, fast write times, a larger resistance ratio (R-Ratio), and low power consumption. Despite the numerous advantages provided by RRAM, significant challenges still need to be addressed, such as resistance variations during fabrication and resistance drift during operation. This variation, which affects retention and the cycle, can lead to resistance degradation, resulting in a reduced the R-ratio (RHRS/RLRS) of ReRAM. Additionally, this resistance variation affects reference cells composed of ReRAM unit cells. Furthermore, resistance degradation can also affect the Bit-line voltage (VBL) during the read operation. Therefore, a low VBL is necessary to prevent this. However, maintaining a low VBL raises concerns about margin and delay. The proposed new sense amplifiers effectively address this variation. This first study proposes a reliable current sense amplifier assisted with dynamic reference (DR-CSA) to enhance sensing margin and robustness. The proposed sensing circuit detects a slight voltage change through capacitive coupling and adjusts the reference current based on the cell states (RHRS ,RLRS) to enhance the sensing margin. This second study introduces a novel time-based sensing (TBS) scheme for enhancing the speed and robustness during the operation and extends from single-level cells (SLC) to multi-level cells (MLC). In the proposed time-based sensing scheme, the bit line (BL) current is converted into a time delay based on cell states using the current-to-time converter (CTC). The resulting distinct time delays are compared to generate digital data. Additionally, The proposed sensing scheme executes sensing operations without using both a reference array and reference generator for reference current or reference voltage, which are required in a conventional current sense amplifier (CSA) or voltage sense amplifier (VSA). The last study introduces a novel hybrid cell-to-cell, referenceless sensing scheme. Since the proposed novel hybrid sensing scheme directly compares cell-to-cell, it requires no analog reference or generator, as is used in conventional voltage-mode schemes or current-mode schemes. Furthermore, the proposed scheme reads 2-bit data during the sensing process simultaneously and is compatible with two load modes: both voltage mode and current mode.

Memories are made of this

Certain NAND flash-based storage devices are not equipped with dynamic random access memory (DRAM) for holding the whole mapping table, due to the constraints of chip size and the cost, such as secure digital cards. Such DRAM-less flash memory can load only a subset of frequently accessed mapping table entries into a limited-capacity, on-board static random access memory (SRAM) cache, to expedite address translation. To improve the use efficiency of the SRAM cache, this paper proposes to prefetch mapping table entries into the cache according to their locality . Then, it can minimize the number of translation page reads at the flash array caused by loading the required entries, thus improving I/O performance. Specifically, we use the indicator of runs test to reflect the locality of mapping table entries on the same translation page. When processing a missed mapping entry, it determines whether adjacent mapping entries accompanying the missed one should be loaded into the cache or not, on the basis of the runs of the target translation page. Consequently, subsequent requests requiring access to these mapping entries can be quickly responded to with the cached ones, instead of reading the target translation pages. In addition, we support cache management based on the runs test of the mapping entries to further improve the cache hit ratio. Experimental results show that our proposal can increase the hit ratio of mapping table entries by 39.4 % and reduce overall I/O latency by 23.4 % on average, in contrast to state-of-the-art schemes.

This chapter contains sections titled: Introduction Static Random Access Memories (SRAMs) Dynamic Random Access Memories (DRAMs) This chapter contains sections titled: References ]]>

Since first proposed by Gordon Moore (an Intel founder) in 1965, his law [107] that the number of transistors on microprocessors doubles roughly every one to two years has proven remarkably astute. Its corollary, that central processing unit (CPU) performance would also double every two years or so has also remained prescient. Figure 1.1 shows Intel microprocessor data on the number of transistors beginning with the 4004 in 1972. Figure 1.2 indicates that when one includes multi-processor machines and algorithmic development, computer performance is actually better than Moore’s 2-year performance doubling time estimate. Alas, however, in recent years there has developed a disagreeable mismatch between CPU and memory performance: CPUs now outperform memory systems by orders of magnitude according to some reckoning [71]. This is not completely accurate, of course: it is mostly a matter of cost. In the 1980s and 1990s, Cray Research Y-MP series machines had well balanced CPU to memory performance. Likewise, NEC (Nippon Electric Corp.), using CMOS (see glossary, Appendix F) and direct memory access, has well balanced CPU/Memory performance. ECL (see glossary, Appendix F) and CMOS static random access memory (SRAM) systems were and remain expensive and like their CPU counterparts have to be carefully kept cool. Worse, because they have to be cooled, close packing is difficult and such systems tend to have small storage per volume. Almost any personal computer (PC) these days has a much larger memory than supercomputer memory systems of the 1980s or early 1990s. In consequence, nearly all memory systems these days are hierarchical, frequently with multiple levels of cache. Figure 1.3 shows the diverging trends between CPUs and memory performance. Dynamic random access memory (DRAM) in some variety has become standard for bulk memory. There are many projects and ideas about how to close this performance gap, for example, the IRAM [78] and RDRAM projects [85]. We are confident that this disparity between CPU and memory access performance will eventually be tightened, but in the meantime, we must deal with the world as it is.

A low power CMOS Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGA) architecture is being presented in this paper. The architecture presented here is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. This architecture employs the fast and low-power SRAM blocks that are based on 10T SRAM cells. These blocks are employed in fast access of the configuration bits by using the shadow SRAM technique. The dynamic reconfiguration delay is being hidden behind the computation delay through the use of shadow SRAM cells. The combined effect of both the SRAM memory cells and the shadow SRAM scheme enables to support in reducing the delay and also to achieve reduced power consumption. Experimental results show reduced delay of about 8.035ns and power consumption of about 0.015W for the 10T SRAM memory cell with an overhead in area, relative to 4T and 6T SRAM cells. Also, the experimental results include the values of delay of about 8.979ns and power consumption of about 0.052W, achieved for the LB of FPGA architecture which employs CMOS SRAMs using the 10T SRAM memory cells in it.