Memories are made of this

Journaling techniques play an important role in addressing the reliability issue of filesystems caused by the volatile dynamic random access memory (DRAM)-based buffer cache. However, journaling techniques introduce a large number of extra storage writes, which greatly degrades system performance, especially for mobile devices. Emerging nonvolatile memory (NVM) technologies bring a new perspective of solving the write amplification issue caused by journaling. By adopting NVM as the buffer cache, the committed data can be maintained in NVM before being written back to the storage, thus, eliminating the journaling overhead. However, simply utilizing NVM as the buffer cache suffers from the limited lifetime and the relatively longer write latency of NVM. In this paper, we present a hybrid buffer cache architecture, named UniBuffer, by combing NVM with dynamic random access memory (DRAM) to reduce the journaling overhead and overcome the inherent constraints of NVM. In UniBuffer, we first propose a journaling-aware page management (JAPM) policy to smartly allocate data to DRAM and NVM pages. JAPM puts infrequently updated data in NVM to reduce the journaling overhead and frequently updated data in DRAM to improve the write performance and lifetime of the hybrid buffer cache. In addition, since data in one journaling transaction may be dispersed in NVM and DRAM simultaneously, different committing policies are required for different storage media, respectively. In order to guarantee the atomicity of the transaction execution in the hybrid cache architecture, a partial in-place commit (PIPC) journaling scheme is proposed to coordinate different committing patterns for NVM and DRAM. We have implemented the proposed techniques on Linux 3.14.52 and measured the performance with representative I/O-intensive benchmarks. The experimental results show that our scheme effectively improves the I/O performance compared with the ext4 filesystem and prolongs the lifetime of the hybrid buffer cache compared with the union of buffer cache and journaling (UBJ) scheme.

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The traditional dynamic random-access memory (DRAM) storage medium can be integrated on chips via modern emerging 3D-stacking technology to architect a DRAM shared cache in multicore systems. Compared with static random-access memory (SRAM), DRAM is larger but slower. In the existing research, a lot of work has been devoted to improving the workload performance using SRAM and stacked DRAM together in shared cache systems, ranging from SRAM structure improvement to optimizing cache tags and data access. However, little attention has been paid to designing a shared cache scheduling scheme for multiprogrammed workloads with different memory footprints in multicore systems. Motivated by this, we propose a hybrid shared cache scheduling scheme that allows a multicore system to utilize SRAM and 3D-stacked DRAM efficiently, thus achieving better workload performance. This scheduling scheme employs (1) a cache monitor, which is used to collect cache statistics; (2) a cache evaluator, which is used to evaluate the cache information during the process of programs being executed; and (3) a cache switcher, which is used to self-adaptively choose SRAM or DRAM shared cache modules. A cache data migration policy is naturally developed to guarantee that the scheduling scheme works correctly. Extensive experiments are conducted to evaluate the workload performance of our proposed scheme. The experimental results showed that our method can improve the multiprogrammed workload performance by up to 25% compared with state-of-the-art methods (including conventional and DRAM cache systems).

In the era of rapidly advancing technology, the limitations of conventional memory architectures have become a significant bottleneck in meeting the growing demands for data storage and processing. Emerging non-volatile memory technologies are increasingly closing the performance gap between traditional memory and storage solutions, driving innovations in memory cell design. This review provides an overview of conventional memory types, such as static random-access memory (SRAM), dynamic random-access memory (DRAM), and Flash memory, alongside emerging prototype memories like resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), and phase-change memory (PCM). Emerging technology nowadays have a wide range of applications. Resistive random-access memory and spin torque transfer random access memory are the most promising memory for in-memory computing which is advanced beyond conventional von Neumann system, neuromorphic computing mimic human’s brain structure. Internet of things devices and wireless sensor devices make use of the low power consumption memory, and the security is provided by the stochasticity nature of random-access memory which is not desired and is considered as a challenge for memory cell.

In the era of rapidly advancing technology, the limitations of conventional memory architectures have become a significant bottleneck in meeting the growing demands for data storage and processing. Emerging non-volatile memory technologies are increasingly closing the performance gap between traditional memory and storage solutions, driving innovations in memory cell design. This review provides an overview of conventional memory types, such as static random-access memory (SRAM), dynamic randomaccess memory (DRAM), and Flash memory, alongside emerging prototype memories like resistive randomaccess memory (RRAM), magnetoresistive randomaccess memory (MRAM), and phase-change memory (PCM). Emerging technology nowadays have a wide range of applications. Resistive random-access memory and spin torque transfer random access memory are the most promising memory for in-memory computing which is advanced beyond conventional von Neumann system, neuromorphic computing mimic human’s brain structure. Internet of things devices and wireless sensor devices make use of the low power consumption memory, and the security is provided by the stochasticity nature of randomaccess memory which is not desired and is considered as a challenge for memory cell.

Representatively, memory has been limitedly used in advances, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Flash Memory. However, nowadays, memory is widely used in smartphones, automobiles, and the Internet of Things (IoT) in everyday electronic devices. Furthermore, there is currently a growing need for high-density memory in terms of size and energy efficiency due to increasing data and computation demands. Non-volatile Memories (NVMs) are promising candidates for achieving fast processing speeds, high data storage density, and energy efficiency because emerging NVMs (STT-MRAM, PCM, ReRAM) offer more of these advantages compared to conventional memory. Among NVMs, ReRAM boasts advantages such as non-volatility, fast write times, a larger resistance ratio (R-Ratio), and low power consumption. Despite the numerous advantages provided by RRAM, significant challenges still need to be addressed, such as resistance variations during fabrication and resistance drift during operation. This variation, which affects retention and the cycle, can lead to resistance degradation, resulting in a reduced the R-ratio (RHRS/RLRS) of ReRAM. Additionally, this resistance variation affects reference cells composed of ReRAM unit cells. Furthermore, resistance degradation can also affect the Bit-line voltage (VBL) during the read operation. Therefore, a low VBL is necessary to prevent this. However, maintaining a low VBL raises concerns about margin and delay. The proposed new sense amplifiers effectively address this variation. This first study proposes a reliable current sense amplifier assisted with dynamic reference (DR-CSA) to enhance sensing margin and robustness. The proposed sensing circuit detects a slight voltage change through capacitive coupling and adjusts the reference current based on the cell states (RHRS ,RLRS) to enhance the sensing margin. This second study introduces a novel time-based sensing (TBS) scheme for enhancing the speed and robustness during the operation and extends from single-level cells (SLC) to multi-level cells (MLC). In the proposed time-based sensing scheme, the bit line (BL) current is converted into a time delay based on cell states using the current-to-time converter (CTC). The resulting distinct time delays are compared to generate digital data. Additionally, The proposed sensing scheme executes sensing operations without using both a reference array and reference generator for reference current or reference voltage, which are required in a conventional current sense amplifier (CSA) or voltage sense amplifier (VSA). The last study introduces a novel hybrid cell-to-cell, referenceless sensing scheme. Since the proposed novel hybrid sensing scheme directly compares cell-to-cell, it requires no analog reference or generator, as is used in conventional voltage-mode schemes or current-mode schemes. Furthermore, the proposed scheme reads 2-bit data during the sensing process simultaneously and is compatible with two load modes: both voltage mode and current mode.

SRAM (Static Random Access Memory) is one of the type of memory which holds the data bit without periodic refreshment. Compared with DRAM (Dynamic Random Access Memory) which requires periodic refreshment of data bit stored in it. Unlike Dynamic RAM, Static RAM uses a flip-flop circuit to store each data bit, whereas Dynamic RAM uses a capacitor to store the data bit. But capacitor has tendency of losing charge which requires periodic refreshment. Thus SRAM perform better and have more stability than DRAM especially in idle state. In this work, we analysed the performance of the SRAM cell which are built with different field effect transistors and calculated the Write and Read delays, PDP (Power Delay Product) and Static Noise Margin (SNM) for all types of transistors. SRAM cell which is based on the CNT technology with optimized parameters of CNT density, CNT diameter and CNTFET flat band voltage has the better performance and stability compared with other device technologies. Optimized CNTFET SRAM cell compared with the MOSFET based SRAM the write and read delays are improved by 85.8% and 94.3% respectively. All the simulations have been carried out using HSPICE tool for 32nm technology node.

Non-volatile memory (NVM) provides a scalable and power-efficient solution to replace dynamic random access memory (DRAM) as main memory. However, because of the relatively high latency and low bandwidth of NVM, NVM is often paired with DRAM to build a heterogeneous memory system (HMS). As a result, data objects of the application must be carefully placed to NVM and DRAM for the best performance. In this paper, we introduce a lightweight runtime solution that automatically and transparently manages data placement on HMS without the requirement of hardware modifications and disruptive change to applications. Leveraging online profiling and performance models, the runtime solution characterizes memory access patterns associated with data objects, and minimizes unnecessary data movement. Our runtime solution effectively bridges the performance gap between NVM and DRAM. We demonstrate that using NVM to replace the majority of DRAM can be a feasible solution for future HPC systems with the assistance of a software-based data management.

Smoke can cause interruptions and upsets in active electronics. Because nuclear power plants are replacing analog with digital instrumentation and control systems, qualification guidelines for new systems are being reviewed for severe environments such as smoke and electromagnetic interference. Active digital systems, individual components, and active circuits have been exposed to smoke in a program sponsored by the U.S. Nuclear Regulatory Commission. The circuits and systems were all monitored during the smoke exposure, indicating any immediate effects of the smoke. The results of previous smoke exposure studies have been reported in various publications. The major immediate effect of smoke has been to increase leakage currents and to cause momentary upsets and failures in digital systems. This paper presents new results from conformal coatings, memory chips, and hard drive tests.The best conformal coatings were found to be polyurethane, parylene, and acrylic (when applied by dipping). Conformal coatings can reduce smoke-induced leakage currents and protect against metal loss through corrosion. However conformal coatings are typically flammable, so they do increase material flammability. Some of the low-voltage biased memory chips failed during a combination of high smoke and high humidity. Typically, smoke along with heat and humidity is expected during fire, rather than smoke alone. Thus, due to high sensitivity of digital circuits to heat and humidity, it is hypothesized that the impact of smoke may be secondary.Low-voltage (3.3-V) static random-access memory (SRAMs) were found to be the most vulnerable to smoke. Higher bias voltages decrease the likelihood of failure. Erasable programmable read-only memory (EPROMs) and nonvolatile SRAMs were very smoke tolerant. Failures of the SRAMs occurred when two conditions were present: high density of smoke and high humidity. As the high humidity was present for only part of the test, the failures were intermittent. All of the chips that failed during the test recovered after enough venting.Hard disks were tested in severe environments but did not fail during the 2 h of monitoring.While the results of the tests documented in this report confirm that digital circuits can indeed be vulnerable to smoke, there is currently no practical, repeatable testing methodology, so it is not feasible to assess smoke susceptibility as part of environmental qualification. As a result, the most reasonable approach to minimizing smoke susceptibility is to employ design, implementation, and procedural practices that can reduce the possibility of smoke exposure and enhance smoke tolerance. Traditional approaches to mitigate its effects in digital safety instrumentation and control, such as redundancy, separation, defense in depth, as well as adherence to standards (e.g., the Institute of Electrical and Electronics Engineers’ IEEE 384) and the Code of Federal Regulations Appendix R of 10 CFR 50, should continue to be applied.

The discovery of giant magnetoresistance (GMR) in magnetic multilayers (Baibich et al., 1988) and of tunnel magnetoresistance (TMR) in metal/insulator junctions (Julliere, 1975) has marked the beginning of spin electronics, which makes use of the electron’s spin as an additional degree of freedom, thus enabling novel phenomena and devices to be imagined. The GMR spin valves (Dieny et al., 1991; Parkin, 1993) have already been integrated in many functional devices like magnetic read heads, angle and position sensors and low-capacity random access memories (RAM). The TMR tunnel junctions are mainly proposed for non-volatile magnetic memories (MRAM) which combine all the advantages of conventional memories such as DRAM (dynamic RAM), SRAM (static RAM) or flash: short access time, non-volatility, insensibility to ionizing radiation, high density, infinite cyclabilty. Major IC manufacturers are now ready to launch the first fully functional prototypes.

The eleven papers in this special section focus on both system- and circuit-level aspects of emerging memory and storage technologies. The overwhelmingly increasing demand for both storage and computation necessitates revisiting the traditional memory subsystems used in processors and storage systems to take advantage of emerging memory technologies. Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) have been ubiquitously used for decades as main memory and as on-chip cache, respectively. Scaling and power issues of these traditional memory technologies have led to significant investment in emerging memory technologies. On the other hand, fundamental limitations of mechanical disk drives have brought great attention to further explore the design space of solid-state drives (SSDs). The promising features of emerging memory technologies such as low power consumption, increased performance, lower susceptibility to particle strikes, and higher bit density have prompted researchers to seek new organizations in the different memory-hierarchy levels, to propose new circuitry and algorithms to improve performance and reduce power consumption, and to develop new schemes to enhance system reliability.

This chapter describes the basic properties of various computer memories. Historical evolution of the roles of non-volatile functionalities in computer architecture is discussed to explain recent rejuvenating interest in new non-volatile memory technologies. Next, required properties for memories, such as scalability, access speed, power consumption, are discussed referring to those of current main-stream memories, i.e., dynamic random access memory (DRAM), static RAM, and NAND flash memory. Then, histories, working principles, and properties of spin-transfer torque magnetoresistive RAM, resistive RAM, phase change RAM, ferroelectric RAM, and NOR flash memory are described. Finally, possible positioning of these various non-volatile memories in future computer architecture are discussed.

ABSTRACTFog computing requires a large main memory capacity to decrease latency and increase the Quality of Service (QoS). However, dynamic random access memory (DRAM), the commonly used random access memory, cannot be included into a fog computing system due to its high consumption of power. In recent years, non-volatile memories (NVM) such as Phase-Change Memory (PCM) and Spin-transfer torque RAM (STT-RAM) with their low power consumption have emerged to replace DRAM. Moreover, the currently proposed hybrid main memory, consisting of both DRAM and NVM, have shown promising advantages in terms of scalability and power consumption. However, the drawbacks of NVM, such as long read/write latency give rise to potential problems leading to asymmetric cache misses in the hybrid main memory. Current last level cache (LLC) policies are based on the unified miss cost, and result in poor performance in LLC and add to the cost of using NVM. In order to minimize the cache miss cost in the hybrid main memory, we propose a cost aware cache replacement policy (CACRP) that reduces the number of cache misses from NVM and improves the cache performance for a hybrid memory system. Experimental results show that our CACRP behaves better in LLC performance, improving performance up to 43.6% (15.5% on average) compared to LRU.

Asymmetry in read/write access latencies, which leads to issues of blocking writes and low throughput performance, is a common challenge impeding the integration of emerging nonvolatile memory technologies into high-performance computing systems. Approaches based on multiporting and virtually pipelined architectures, which have been studied in static random access memory (SRAM)/dynamic random access memory (DRAM)/hybrid-SRAM/DRAM memory systems for high throughput performance, provide an attractive means to overcome these challenges through innovations spanning the memory cell to architecture levels. This paper describes a virtually pipelined memory architecture built on a two-port phase change memory (PCM) substrate for high-performance networking applications. The proposed two-port PCM cell significantly reduces the probability of bank conflicts due to blocking writes. We comprehensively evaluate the two-port cell design in terms of programming current, voltage pumping for access transistors, and area overhead. We also propose a two-port PCM bank design to provide the large bandwidth and bank parallelism critical for high-performance networking applications. Furthermore, the virtually pipelined architecture is implemented at the memory controller level, eliminating the extra delay of read requests due to the asymmetrical access latency through separate reservation tables for read and write requests. We analyze the performance of this architecture using queuing theory and statistical information obtained by processing packet traces using PacketBench, and show that the proposed innovations can reduce the expected read (write) delay by 12– $40\times $ (up to 14%) over conventional single-port PCM for 110%–170% additional area.

A dynamic oxide semiconductor random access memory (DOSRAM) array that achieves reduction in storage capacitance (Cs) and decrease in refresh rate has been fabricated by using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) transistor (L = 60 nm) with an extremely low off-state current. We have confirmed that this array, composed of cells that include a CAAC-OS transistor with W/L = 40 nm/60 nm using InGaZnO and a 3.9 fF storage capacitor, operates with write and read times of 5 ns. Therefore, DOSRAM can ensure sufficient Cs while maintaining operation speed comparable to that of dynamic random access memory (DRAM). We have found that the read signal voltage of DOSRAM is changed by approximately 30 mV after 1 h at 85 °C. Thus, DOSRAM is a promising replacement for DRAM.