Unimem: Runtime Data Management on Non-Volatile Memory-Based Heterogeneous Main Memory for High Performance Computing

Journaling techniques play an important role in addressing the reliability issue of filesystems caused by the volatile dynamic random access memory (DRAM)-based buffer cache. However, journaling techniques introduce a large number of extra storage writes, which greatly degrades system performance, especially for mobile devices. Emerging nonvolatile memory (NVM) technologies bring a new perspective of solving the write amplification issue caused by journaling. By adopting NVM as the buffer cache, the committed data can be maintained in NVM before being written back to the storage, thus, eliminating the journaling overhead. However, simply utilizing NVM as the buffer cache suffers from the limited lifetime and the relatively longer write latency of NVM. In this paper, we present a hybrid buffer cache architecture, named UniBuffer, by combing NVM with dynamic random access memory (DRAM) to reduce the journaling overhead and overcome the inherent constraints of NVM. In UniBuffer, we first propose a journaling-aware page management (JAPM) policy to smartly allocate data to DRAM and NVM pages. JAPM puts infrequently updated data in NVM to reduce the journaling overhead and frequently updated data in DRAM to improve the write performance and lifetime of the hybrid buffer cache. In addition, since data in one journaling transaction may be dispersed in NVM and DRAM simultaneously, different committing policies are required for different storage media, respectively. In order to guarantee the atomicity of the transaction execution in the hybrid cache architecture, a partial in-place commit (PIPC) journaling scheme is proposed to coordinate different committing patterns for NVM and DRAM. We have implemented the proposed techniques on Linux 3.14.52 and measured the performance with representative I/O-intensive benchmarks. The experimental results show that our scheme effectively improves the I/O performance compared with the ext4 filesystem and prolongs the lifetime of the hybrid buffer cache compared with the union of buffer cache and journaling (UBJ) scheme.

ABSTRACTFog computing requires a large main memory capacity to decrease latency and increase the Quality of Service (QoS). However, dynamic random access memory (DRAM), the commonly used random access memory, cannot be included into a fog computing system due to its high consumption of power. In recent years, non-volatile memories (NVM) such as Phase-Change Memory (PCM) and Spin-transfer torque RAM (STT-RAM) with their low power consumption have emerged to replace DRAM. Moreover, the currently proposed hybrid main memory, consisting of both DRAM and NVM, have shown promising advantages in terms of scalability and power consumption. However, the drawbacks of NVM, such as long read/write latency give rise to potential problems leading to asymmetric cache misses in the hybrid main memory. Current last level cache (LLC) policies are based on the unified miss cost, and result in poor performance in LLC and add to the cost of using NVM. In order to minimize the cache miss cost in the hybrid main memory, we propose a cost aware cache replacement policy (CACRP) that reduces the number of cache misses from NVM and improves the cache performance for a hybrid memory system. Experimental results show that our CACRP behaves better in LLC performance, improving performance up to 43.6% (15.5% on average) compared to LRU.

There are many researches and developments on byte accessible non-volatile memory (NVM). Byte accessible NVM can be used as not only storage but also main memory. Non-volatile main memory has two significant merits: reducing power consumption of main memory, flexible system standby and fast resume. However, NVM has bottlenecks in writing and limitation on the number of writing. To overcome this problem, there are some researches on hybrid memory architectures, which combine NVM and DRAM. On hybrid memory architectures, it needs to collect program characteristics of write access and allocate DRAM or NVM based on that characteristics. Previous works proposed to collect and allocate at hardware level or operating system level. At hardware or OS level, memory allocators can collect writing information of wide range of processes. However, they do not know contents of written data, thus they cannot allocate memory based on data characteristics. To solve this problem, we propose a method to obtain characteristics of writing and assign DRAM or NVM based on that information in previous work. The method applies write barrier of language runtimes to collect writing characteristics. This paper describes modification of our previous work and preliminary analysis for implementation the method on Jikes RVM.

Byte addressable non-volatile (NV) memory, such as STT-RAM, MRAM, and PCM, is the next generation memory that can be used as both main memory and secondary storage. While it can persistently store data without power supply, its access speed is comparable to DRAM. While there have been the active researches on its use for either main memory or secondary storage, these researches were conducted independently. This paper presents the integration methods of the main memory and file system management for NV memory, so that it can be used as both main memory and storage. The presented methods use a file system as their basis for the NV memory management; thus, the internal data structures of a file system can have impacts upon the performance of the integration methods. We implemented the proposed methods in the Linux kernel, and performed the evaluation on a system emulator. The evaluation results show that 1) the proposed methods can perform comparably to the existing DRAM memory allocator and significantly better than the page swapping, 2) their performance is affected by the internal data structures of a file system, and 3) the data structures appropriate for traditional hard disk drives do not always work effectively for byte addressable NV memory.

Register allocation for write activity minimization on non-volatile main memory for embedded systems

Dynamic Random Access Memory (DRAM) has been prevalent over the past few decades as main memory component. The demand of higher memory capacity is increasing continuously, while scaling of DRAM is reaching its boundaries. As we scale DRAM to smaller feature size, difficulties in fabrication, leakage power, and energy consumption become significant. Therefore, memory technologies, which have better scalability feature, will be the future of memory systems. To overcome these limitations, search for a new memory technology is necessary and Phase Change Memory (PCM) is the most promising. PCM is non-volatile memory with better scalability and less leakage power than DRAM. It is a resistance-based memory, which doesn't need to be refreshed. PCM suffers more write latency and less write endurance. The write latency of PCM is higher than its read latency by almost 8 times. A large number of researches have been done on reducing write latency of PCM. This research will focus on studying different approaches and techniques in order to reduce write latency on various aspects. Then, techniques employed to reduce write latency of PCM such as PreSET, Partial-SET, Flip-N-Write, two-stage-write, and two-stage-write-inv are introduced. Conclusively, a performance comparison of each technique is discussed.

The gap between processor and memory speeds is one of the greatest challenges that current designers face in order to develop more powerful computer systems. In addition, the scalability of the Dynamic Random Access Memory (DRAM) technology is very limited nowadays, leading one to consider new memory technologies as candidates for the replacement of conventional DRAM. Phase-Change Memory (PCM) is currently postulated as the prime contender due to its higher scalability and lower leakage. However, compared with DRAM, PCM also exhibits some drawbacks, like lower endurance or higher dynamic energy consumption and write latency, that need to be mitigated before it can be used as the main memory technology for the next generation of computers. This work addresses the PCM endurance constraint. For this purpose, we present an analysis of conventional cache replacement policies in terms of the amount of writebacks to main memory that they imply and we also propose some new replacement algorithms for the last-level cache (LLC) with the goal of cutting down the write traffic to memory and consequently, to increase PCM lifetime without degrading system performance. In this paper, we target general purpose processors provided with this kind of non-volatile main memory and we exhaustively evaluate our proposed policies in both single- and multi-core environments. Experimental results show that, on average, compared with a conventional Least Recently Used (LRU) algorithm, some of our proposals manage to reduce the amount of writes to main memory up to 20–30% depending on the scenario evaluated, which leads to memory endurance extensions of up to 20–45%, also reducing the energy consumption in the memory hierarchy by up to 9% and hardly degrading performance.

The non-volatile memory (NVM) has the merits of byte-addressability, fast speed, persistency and low power consumption, which make it attractive to be used as main memory. Commonly, user process dynamically acquires memory through memory allocators. However, traditional memory allocators designed with in-place data writes are not appropriate for the non-volatile main memory (NVRAM) due to the limited endurance. In this article, first, we quantitatively analyze the wear-oblivious of DRAM-oriented designed allocator—glibc malloc and the inefficiency of wear-conscious allocator NVMalloc. Then, we propose WAlloc, an efficient wear-aware manual memory allocator designed for NVRAM: (1) decouples metadata and data management; (2) distinguishes metadata with volatility; (3) redirects the data writes around to achieve wear-leveling; (4) redesigns an efficient and effective NVM copy mechanism, bypassing the CPU cache partially and prefetching data explicitly. Finally, experimental results show that the wear-leveling of WAlloc outperforms that of NVMalloc about 30% and 60% under random workloads and well-distributed workloads, respectively. Besides, WAlloc reduces the average data memory writes in 64 bytes block by 1.5 times comparing with glibc malloc. With the fulfillment of data persistency, cache bypassing NVM copy is better than cache line flushing NVM copy with performance improvement circa 14%.

Dynamic Random Access Memory (DRAM) has been used in main memory design for decades. However, DRAM consumes an increasing power budget and faces difficulties in scaling down for small feature size CMOS processing technologies. Compared to conventional DRAM, emerging phase change random access memory (PRAM) demonstrates superior power efficiency and processing scalability as VLSI technologies and integration density continue to advance. Nevertheless, using nano-scale fabrication technologies will unavoidably introduce design parameter variability in the manufacturing stage. In the past, the impact of process variation (PV) on conventional transistor-based storage cells and combinational logic has been studied extensively. However, the implication of PV on non-volatile memory design using emerging phase change techniques has not been well understood. In this paper, we take the first step toward characterizing the effect of process variation on PRAM and explore PV-aware design techniques. We show that process variation increases the PRAM programming power by 96% and degrades PRAM endurance by 50X. Our proposed circuit and two microarchtiecture techniques with system-level support reduce PRAM power by 44%, 59% and 57% and improve PRAM endurance by 27X, 277X and 268X, relative to PV-affected PRAM design. Moreover, we show that the synergy of the proposed cross-layer approaches, which achieve an average 63% power savings and 13050X endurance improvement over the conventional case, provide an attractive design solution to mitigate the deleterious impact of PV for non-volatile memory in the upcoming nano-scale processing technology era.

While the memory footprints of cloud and HPC applications continue to increase, fundamental issues with DRAM scaling are likely to prevent traditional main memory systems, composed of monolithic DRAM, from greatly growing in capacity. Hybrid memory systems can mitigate the scaling limitations of monolithic DRAM by pairing together multiple memory technologies (e.g., different types of DRAM, or DRAM and non-volatile memory) at the same level of the memory hierarchy. The goal of a hybrid main memory is to combine the different advantages of the multiple memory types in a cost-effective manner while avoiding the disadvantages of each technology. Memory pages are placed in and migrated between the different memories within a hybrid memory system, based on the properties of each page. It is important to make intelligent page management (i.e., placement and migration) decisions, as they can significantly affect system performance.In this paper, we propose utility-based hybrid memory management (UH-MEM), a new page management mechanism for various hybrid memories, that systematically estimates the utility (i.e., the system performance benefit) of migrating a page between different memory types, and uses this information to guide data placement. UH-MEM operates in two steps. First, it estimates how much a single application would benefit from migrating one of its pages to a different type of memory, by comprehensively considering access frequency, row buffer locality, and memory-level parallelism. Second, it translates the estimated benefit of a single application to an estimate of the overall system performance benefit from such a migration.We evaluate the effectiveness of UH-MEM with various types of hybrid memories, and show that it significantly improves system performance on each of these hybrid memories. For a memory system with DRAM and non-volatile memory, UH-MEM improves performance by 14% on average (and up to 26%) compared to the best of three evaluated state-of-the-art mechanisms across a large number of data-intensive workloads.

Dynamic random access memory (DRAM) is used as the main memory in every personal computer, due to its high density, high speed and efficient memory function. The ever-shrinking dimensions of DRAM cells with increasing packing density made the cell's capacitor size to be smaller. For successful operation of DRAM, a large cell capacitance (~ 25 fF) and low leakage current (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> or 1 fA/cell) are required. In a traditional Si-based capacitor, the target cell capacitance has been achieved by increasing the surface area of the capacitor. More recently, innovations have been made by development of the component materials. A metal electrode, TiN or Ru, and a dielectric material with a moderate-k value (k is the relative dielectric constant), such as HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (k ~ 25) and ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (k ~ 40), are being explored in giga-bit scale DRAMs. The minimum achievable t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> is ~ 0.7 nm for ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> which is being used currently in DRAM industry. However, the technology road map for memory devices states that t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> of less than 0.45 nm is necessary for the DRAMs with a design rule of <; 20 nm. Perovskite-based dielectric films such as SrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (STO) and (Ba, Sr)TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> were reported to exhibit k values of several hundreds. However, growth of these films showed very slow growth rate and much more complicated processes than growth of binary oxide with the atomic layer deposition (ALD) technique which is a method of choice for the growth of the dielectric films and electrodes in microelectronic devices. Therefore, material and process innovations are necessary for next generation DRAM capacitors.

Page migration has long been adopted in hybrid memory systems comprising dynamic random access memory (DRAM) and non-volatile memories (NVMs), to improve the system performance and energy efficiency. However, page migration introduces some side effects, such as more translation lookaside buffer (TLB) misses, breaking memory contiguity, and extra memory accesses due to page table updating. In this paper, we propose superpage-friendly page table called SuperPT to reduce the performance overhead of serving TLB misses. By leveraging a virtual hashed page table and a hybrid DRAM allocator, SuperPT performs address translations in a flexible and efficient way while still remaining the contiguity within the migrated pages.

Memories are made of this

Non-volatile memories (NVMs) show great potential in replacing DRAM as the main memory in many embedded systems because of their attractive characteristics such as low cost, high density, and low energy consumption. However, the problem of asymmetric read and write costs has to be addressed before the advantages of NVM can be fully exploited. That is, the cost of write operation is much more expensive than the cost of read operation on NVMs. The existing techniques for loop optimization cannot be used effectively with non-volatile main memory because this special feature is not considered. In this paper, we propose an efficient loop scheduling algorithm, the Rotation with Maximum Bipartite Matching (RMBM) algorithm, to address the problem of expensive write operations on non-volatile main memory for chip multiprocessors (CMPs). It achieves high parallelism for a loop and, at the same time, reduces the number of write operations on NVM. The experimental results show that the RMBM algorithm reduces the number of write activities on NVM by 34.5 % on average compared with the traditional rotation scheduling algorithm. The execution time is reduced by 20.5 %, and the energy consumption is also reduced by 15.03 % on average using the RMBM algorithm. In other words, the average lifetime of NVM can be extended by more than 2 times using the proposed technique.

New non-volatile memory (NVM) technologies, e.g., Phase Change Memory (PCM), are emerging with main features such as byte addressability, cheapness and large size, and will be deployed to serve as main memory. For fast processing of big data, block device drivers have been developed for NVM such that traditional file systems (e.g., EXT4) operated on non-volatile main memory. However, the existing block driver blindly caches pages, which incurs unnecessary access delays. To overcome this drawback, this paper develops a novel block device driver, called NVMBD, for byte-addressable non-volatile main memory. It adopts two methods of processing block I/O requests, i.e., traditional block I/O and BMAP. On the one hand, traditional block I/O reads/writes 512B sectors with multiple load/store instructions. On the other hand, BMAP inserts NVM pages into the page cache tree when processing block I/O requests, which removes the page movement between the page cache and the NVM. BMAP involves in the management of page cache, but it is transparent to file systems. BMAP provides file systems with the DAX-like feature, improving the file system performance. Through comprehensive experiments, we demonstrate that the developed block device driver significantly improves the file access performance.