Bi primitive switching crypto system with key generation mechanism for secure applications

Side-channel analysis (SCA) is launched by exploiting the information leaking from the implementation a cryptographic algorithm, e.g., power consumption information. Recently, deep learning-based SCA techniques have also facilitated SCA against software and hardware implementations of various cryptographic algorithms. In this work, we perform SCA using various deep learning (DL) techniques such as Multi-layered Perceptron (MLP), Convolutional Neural Network (CNN), and Recurrent Neural Network (RNN) on the datasets collected from hardware and software platforms. The objective of this work is to identify the performance of DL techniques in performing SCA for secret key recovery and finding out the best settings for the model to optimize the attack performance in terms of on computation time and SCA efficiency. In our study, we have focused on two open-source AES-128 encryption algorithm databases, ASCAD and DPA contest v2 (DPAv2), where ASCAD database consists of the power traces captured from a software implementation of the AES and DPAv2 database consists of the power traces captured a hardware implementation of the AES. For the first time, we applied hyperparameter tuning with Bayesian Optimization and distributed computing on ASCAD database and we investigated the impact of MLP and RNN along with the distributed computing and hyperparameter tuning with Bayesian optimization on DPAv2 database. Our results show that the CNNs are the best models for performing the attack on software implementation while MLPs are the best for attacking hardware implementation of cryptographic algorithms.

The RFID Technology is widely used in many authentications and a sophisticated application, still having many prospective issues includes privacy and security issues. To resolve these issues, this paper presents an efficient Lightweight cryptographic Block cipher algorithm. The hardware architecture of Tiny Encryption Algorithm (TEA) is designed and which is simple, flexible, fewer computations required and simple key scheduling. To overcome the security attacks in key scheduling on TEA, an Extended TEA (XTEA) is designed, which is having pipelined architecture with parallel computation to improve the throughput and provide better security. The proposed XTEA is in reconfigurable nature, by changing the mode to process encryption or decryption. The TEA and XTEA simulation results are obtained from Xilinx ISE tool on ModelSim 6.5f simulator and implemented on FPGA Platform-Artix-7 with resource constraints like Area, time and power are tabulated. The proposed XTEA is compared with similar existing research approaches like AES-8bit, TinyXTEA1, and Tiny XTEA-3 with an improvement of Area, throughput and Efficiency on same FPGA platform. The proposed XTEA works at the high throughput of 81 Mbps and Efficiency of 0.34 Mbps/Slice.

Cryptographic systems can potentially suffer from various attacks which are a consequence of vulnearability of side channel information to analysis attacks. The nature of digital circuits is prone to electromagnetic and power analysis (EMA and PA) attacks. Interconnects in cryptographic circuits emanate information through electromagnetic signals which can be exploited using EMA. Complementary Metal Oxide Semiconductor (CMOS) circuits are vulnearable to leak of computational information through leakage and dynamic power consumption. Dynamic power consumption of cryptographic engines is a rich source to sink in the data under process. The hardware implementation of cryptographic algorithms undermine the security of encrypted system against non brute-force-attacks. The attackers collect and analyse the leakage information of cryptographic circuits to detect the secrete key. The parameters sensitivity of the device and circuits make the cryptographic engines vulnearable to fault injection and inherent inconsistency of the circuits. Dynamic and static power comprise two major components of power consumption of digital circuits. Both power components vary with data under process. This exhibits power consumption has data dependency in digital circuits. To make noisy power profile, various countermeasures have been proposed against Differential Power Analysis (DPA) attacks. In this research, false glitch cells is proposed to work as a countermeasure to generate random transitions and power spikes to scramble power profile. The mathematical foundation of security implications of false glitch cells against Correlation Power Analysis (CPA) attacks is investigated. Moreoever, the security efficiency of utilizing false glitch cells is verified with different metrics.

There has been a significant rise in internet and wireless device users, raising the need for security to protect consumer data shared over open networks. Field Programmable Gate Arrays (FPGAs) are particularly desirable alternative for hardware implementation of cryptographic algorithm. This paper discusses hardware implementation of AES algorithm on a Field Programmable Gate Array (FPGA) platform with focus on high throughput and low area constraint. In the proposed design, an efficient pipelined architecture for AES encryption/decryption is realized using unrolled and external pipelining techniques. The proposed design is implemented on different families Virtex-5 and Spartan-6 of FPGA platform. This design obtained maximum throughput of 37.57 Gbps and 32.44 Gbps on Virtex-5 and Spartan-6, respectively. Along with throughput, it also got maximum frequency and high throughput per slice with significant number of slices.

Side-Channel Analysis Attacks on Hardware Implementations of Cryptographic Algorithms

Flexible hardware implementations of cryptographic algorithms in the real time applications have been frequently proposed. This paper classifies the state-of-the-art research practices through a Systematic Literature Review (SLR) process. The selected researches have been classified into three design categories: crypto processor, crypto coprocessor and multicore crypto processor. Subsequently, comparative analysis in terms of flexibility, throughput and area is presented. It facilitates the researchers and designers of the domain to select an appropriate design approach for a particular algorithm and/or application.

The main goal of this chapter is to study FPGA devices in the field of secured applications. We mainly address data protection based on a well defined threat model. When dealing with FPGAs at the system level, two kinds of data are of paramount importance: bitstream and external memory. To cover these topics, we first review state of the art FPGA security mechanisms and good practices, followed by performance analysis achievable using hardware implementation of cryptographic algorithms in current FPGAs. We then tackle external memory protection and how FPGAs can provide an efficient solution. Next, we highlight security issues specific to FPGAs, bitstream replay attacks, for example, and suggest solutions to improve bitstream management security, focusing on secure remote updating of FPGA bitstreams. Finally we give the results of a concrete case, i.e., a platform based on an FPGA device. This last section provides both a practical and an industrial point of view that will enable readers to evaluate the pertinence of the solutions proposed.

In order to design efficient hardware implementations of cryptographic algorithms for a particular application, it is often required to explore several architectures in order to select the one that offers the appropriate trade-off between throughput and hardware resources. A natural choice for performing a design space exploration are the Field Programmable Gate Arrays (FPGAs) for being reconfigurable, flexible and physically secure devices. In this paper we explore several architectures for implementing the SHA-512 algorithm based on the loop unrolling technique and analyze their area-performance trade-offs. The analysis consists on unrolling at different levels the main loop which is the most costly part in the SHA-512 algorithm. The resulting hardware architectures are implemented and analyzed in order to identify the critical path and make decisions on the architectural design. The obtained results provide a practical guide to understand the effect of introducing different levels (1, 2, 4, 5, 8) of unrolling in terms of throughput and hardware resources. The hardware architecture 4x that partially unrolls four iterations of the main loop of the SHA-512 algorithm reports the best performance compared against related works, while the 1x architecture exhibits the best efficiency.

Hardware implementations of cryptographic algorithms are still vulnerable to side-channel attacks. Side-channel attacks that are based on multiple measurements of the same operation can be countered by employing masking techniques. In the presence of glitches, most of the currently known masking techniques still leak information during the computation of non-linear functions. We discuss a recently introduced masking method which is based on secret sharing and results in implementations that are provable resistant against first-order side-channel attacks, even in the presence of glitches. We reduce the hardware requirements of this method and show how to derive provable secure implementations of some non-linear building blocks for cryptographic algorithms. Finally, we provide a provable secure implementation of the block cipher Noekeon and verify the results.

Coarse-grained reconfigurable cryptographic logic arrays (CGRCAs) have become an important platform for hardware implementation of cryptographic algorithms due to their good balance between performance and flexibility. However, existing CGRCA architectures suffer from low hardware resource utilization and low performance of cryptographic algorithms with chained operation modes (e.g., CBC mode of block cipher algorithms). In this paper, an efficient design method for highperformance and high-resource-utilization CGRCA is proposed. The structural characteristics, data dependencies, and parallelism of symmetric cryptographic algorithms are analyzed to determine the core design requirements of the CGRCA. Moreover, multi-task interleaved pipelining (MTIP) and virtual-path parallel processing (VPP) techniques are adapted to improve the parallel processing capability of the CGRCA. On this basis, a chord-based CGRCA architectural model is built to guide the hardware structure design of the CGRCA architecture. Finally, a Bayesian-based design space exploration (DSE) method is proposed to accurately and efficiently determine the core design parameters of CGRCA. The experimental results show that the CGRCA architecture based on the proposed design method can significantly improve performance and hardware resource utilization compared with the traditional CGRCA architectures.

Tag's memory can be easily accessed by readers without any type of authentication technique in GEN2 protocol. In this paper, we use security implementation and mutual authentication between tag and reader of three different lightweight ciphers. We used Hummingbird (HB), PRESENT, and Extended Tiny Encryption Algorithm (XTEA) to encrypt the data and implemented all three algorithms to FPGA devices. We finally implemented PRESENT with PUFFIN as a trail and we got better results compared to the former three ciphers based on performance, data blocks and execution time.

The SM4 cryptographic algorithm is one of the standards of commercial cryptographic algorithm in China, which is used widely in the data encryption and other application scenarios for the advantages of less resources and fast speed. The attackers attack the first and last round of SM4 algorithm generally in the side channel attack. The number of the invalid random rounds before and after the SM4 cryptographic algorithm can make the side channel information collected by the attacker invalid in order to resist the side channel attack; At the same time, the multistage pipelining method is adopted to realize the SM4 cryptographic algorithm at the high speed, that is, four rounds of operations are realized every cycle, and one SM4 grouping operation is completed in eight cycles. The implementation results of the FPGA show that the clock frequency of SM4 cipher operation is up to 100MHz and the throughput rate under ECB mode is up to 1.6gbps, which has the advantages of high performance and anti-side channel attack.

This paper presents a single chip efficient FPGA implementation of RSA and DES for Digital Envelope Scheme that targets the Altera Apex 20KE EP20k200EBC356. Implementation of cryptographic algorithms on programmable devices like FPGAs run much faster than on software while preserving physical security of hardware solutions. The high throughput in the implementation of cryptographic algorithms for digital envelope scheme is achieved by means of exploiting the parallelism present in the DES and RSA operations as well as the features of Altera Apex 20KE device family which best suit for system-on-a-programmable-chip (SOPC) applications. The parallelized single chip implementation of DES and RSA for performing the Encryption/Decryption for the Digital envelope scheme offers a throughput of 3.5 Gbits/sec at a system clock rate of 54.7 MHz. This implementation even provides a means for using the DES and RSA separately.

An offline E-cash system is presented that offers appreciably greater security and better privacy than currently considered E-cash system with similar functionality. Most off-line E-cash systems use the temper-resistant IC card which controls an E-cash issued by the card issuer. Offline E-cash system based on IC card has the threats of overspending, double spending, forgery E-cash, altering/eavesdropping transaction contents, etc. To prevent the above threats, there have been a lot of technical discussions of the security requirements for theoretical offline E-cash protocols based on IC card. However, there has been little attention paid to the security requirements for practical offline E-cash system based on IC card including entity authentication, key management, implementation of cryptographic algorithm, etc. Thus, this paper describes the security requirements for cryptographic algorithms, integrity for implementation of cryptographic algorithm, authentication module, key management, and E-cash protocols

Quantum computing represents a transformative advancement in computational power, with profound implications for cryptographic systems. This paper explores the intersection of quantum computing and cryptography, examining the potential for quantum computers to both break traditional cryptographic algorithms and enable new forms of secure communication. Classical cryptographic systems, such as RSA and ECC, rely on the computational difficulty of problems like integer factorization and discrete logarithms. However, quantum algorithms, notably Shor's algorithm, can solve these problems exponentially faster than the best-known classical algorithms, posing a significant threat to the security of current cryptographic practices. This vulnerability necessitates the development and implementation of quantum-resistant algorithms to ensure data security in a post-quantum world. The paper reviews the state-of-the-art in quantum-resistant cryptographic algorithms, including lattice-based, hash-based, code-based, and multivariate polynomial cryptography. These algorithms are analyzed for their security properties, efficiency, and practicality for real-world deployment. Additionally, the paper discusses the ongoing standardization efforts led by organizations such as NIST, which are crucial for establishing widely accepted quantum-safe cryptographic protocols. Beyond the threat posed by quantum computing, this paper also highlights the potential benefits quantum computing can bring to cryptographic systems. Quantum Key Distribution (QKD) is one such advancement, offering theoretically unbreakable encryption by leveraging the principles of quantum mechanics. QKD enables secure communication channels that are immune to any computational advances, including those of quantum computers, by ensuring that any attempt at eavesdropping can be detected. The practical implementation challenges of QKD and other quantum cryptographic protocols are also addressed, including issues related to transmission distance, error rates, and integration with existing communication infrastructures. Experimental results from recent QKD trials are presented, showcasing significant progress in extending the viability of quantum-secure communication over long distances. Furthermore, the paper delves into the hybrid approaches combining classical and quantum cryptographic techniques. These approaches aim to leverage the strengths of both paradigms to enhance security and performance. For instance, hybrid protocols might use classical encryption for bulk data transfer, supplemented by quantum techniques for key exchange, thereby ensuring robust security even against future quantum adversaries. In conclusion, while quantum computing poses substantial risks to existing cryptographic systems, it also offers novel opportunities for creating highly secure communication protocols. The transition to quantum-safe cryptography is imperative to protect sensitive information in the quantum era. This paper underscores the urgency of advancing quantum-resistant cryptographic research, promoting international collaboration for standardization, and exploring innovative applications of quantum technologies in cryptography. Continued research and development in these areas are essential to stay ahead of the evolving threat landscape and harness the full potential of quantum computing for secure communications.