Реалізація криптографічних алгоритмів на основі ПЛІС для цифрових розподілених систем

In this paper, the implementation and reconfigurable feature of RSA and AES cryptographic algorithm are analyzed. On the basis of the Reconfigurable design of this two algorithms, Reconfigurable RSA and AES hardware architecture is designed to fit four different key length of 256bit, 512bit, 1024bit, 2048bit for RSA, and three different key length of 128bit, 192bit, and 256bit for AES. The reconfigurable design and testing are carried out on FPGA, the results showed that it is able to meet the high-performance information security systems encryption algorithm on the speed requirement.

As one of biometric identification technologies, speaker recognition shows better application prospects in many fields. At present, the implementation of speaker recognition algorithm on the hardware is mostly based on System on a Programmable Chip(SOPC) platform of Field Programmable Gate Array(FPGA) with Nios II Intellectual Property(IP) core. And the algorithm can be selected and optimized effectively on SOPC. However the high-speed and parallel operation of FPGA can't be fully utilized. By researching and analyzing the speaker recognition algorithm, a FPGA-based speaker recognition method is presented in this paper. This method includes the Voice Active Detection (VAD), Mel Frequency Cepstrum Coefficient (MFCC) extraction and Vector Quantization (VQ) recognition algorithm. By using the technology such as Ping-pang operation, Pipeline and module reuse, it makes full use of FPGA's speed. After testing, this method can effectively meet the requirement of real-time data processing.

Impossible differential cryptanalysis of FBC-128

Since Power Analysis on smart cards was introduced by Paul Kocher [], many countermeasures have been proposed to protect implementations of cryptographic algorithms. In this paper we propose a new protection principle: the transformed masking method. We apply this method to protect two of the most popular block ciphers: DES and the AES Rijndael. To this end we introduce some transformed S-boxes for DES and a new masking method and its applications to the non-linear part of Rijndael.

Around 1970 Intel discovered it could put 2,000 transistorsor perhaps a few moreon a single NMOS chip. In retrospect, this may be said to mark the beginning of very large-scale integration (VLSI), ...

An offline E-cash system is presented that offers appreciably greater security and better privacy than currently considered E-cash system with similar functionality. Most off-line E-cash systems use the temper-resistant IC card which controls an E-cash issued by the card issuer. Offline E-cash system based on IC card has the threats of overspending, double spending, forgery E-cash, altering/eavesdropping transaction contents, etc. To prevent the above threats, there have been a lot of technical discussions of the security requirements for theoretical offline E-cash protocols based on IC card. However, there has been little attention paid to the security requirements for practical offline E-cash system based on IC card including entity authentication, key management, implementation of cryptographic algorithm, etc. Thus, this paper describes the security requirements for cryptographic algorithms, integrity for implementation of cryptographic algorithm, authentication module, key management, and E-cash protocols

Ensuring security to the information transaction is a major challenge in the communication environment. The choice to guarantee the data transfer using a ciphering algorithm leads to high cost and complexity. The software-based implementations of cryptographic algorithms are easy to design and operate, but the performance penalty paid is high. The hardware implementations of cryptographic algorithms are considered as a task involving intensive computation and evaluation. Microcontroller-based applications for the same prove to be good solutions to the problem for cost-optimized applications. This paper aims to design, implement, and test a microcontroller (AT89c51)-based crypto system using the Tiny Encryption Algorithm and the Extended Tiny Encryption Algorithm as security primitives. The real-time data can be processed with scheduling of the primitives and the context switching between the primitives reduces the probability of being attacked. The keys for the crypto system are generated using internal timers of the microcontroller. The data to be transmitted are encrypted with any one of the security primitives with the generated key and the encrypted data are transmitted both in wired and wireless modes. At the receiving end, the received data are decrypted and the performance of the crypto system is evaluated on the basis of throughput, code size used, and execution time.

In a white-box context, an attacker has full access to the execution environment and the implementation of cryptographic algorithms. Dedicated white-box ciphers, such as WEM and SPNbox, provide incompressibility and key extraction protections in this context, at the cost of increased memory usage and performance loss compared to standard ciphers. Even when a pure white-box threat model is not warranted, the use of incompressible lookup tables can be helpful in deterring side-channel attacks. In this paper we present a simple threat model for such scenarios and propose a dedicated cipher, Space-Hard AES, which provides minimal incompressibility guarantees while presenting better performance for ARMv8 implementations than other dedicated ciphers.

Implementations of cryptographic algorithms are vulnerable to Side-Channel Analyses extracting information from the device behaviour. When such an attack targets the manipulation of several, say d, intermediate variables then it is said to be a d th-order one. A privileged way to circumvent this type of attacks is to split any key-dependent variable into n shares, with n > d, and to adapt the internal processing in order to securely operate on these shares. The latter step is often very tricky and few schemes have been proposed which address this issue in a sound way.At Asiacrypt 2012, Balasch et al. proposed a new scheme based on the inner-product sharing introduced the same year by Dziembowski and Faust at TCC. This scheme is the first one to aim at provable security in two different security models: the continuous bounded-range leakage model and the d th-order side-channel security model (sometimes called d-probing model).In this paper, we contradict the d th-order security claim by exhibiting some first-order information leakages. Namely, we show that some intermediate variables of the scheme depend on secret information whatever the number of shares. This result is of importance since this kind of flaw is considered as a dead-end point when evaluating the practical security of an implementation. To illustrate the effectiveness of the flaw, we perform an information theoretic evaluation of the first-order leakage and we provide simulation results for a standard side-channel attack against the scheme.KeywordsSecret SharingBlock CipherSecurity ModelIntermediate VariableInformation LeakageThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Since side-channel attacks turned out to be a major threat against implementations of cryptographic algorithms, many countermeasures have been proposed. Amongst them, multiplicative blinding is believed to provide a reasonable amount of security for public-key algorithms. In this article we show how template attacks can be used to extract sufficient information to recover the mask. Our practical experiments verify that one power trace suffices in order to remove such a blinding factor. In the course of our work we attacked a protected Montgomery Powering Ladder implementation on a widely used microcontroller. As a result we can state that the described attack could be a serious threat for public key algorithms implemented on devices with small word size.

Abstract: Cryptographic application plays an important role in wireless communication, especially, a FPGA built-in RFID tag on UHF band (860-960 MHz). The information safety can be obtained by applying suitable and advanced cryptographic algorithm. This paper simulates the installation and implementation of cryptographic algorithm on a FPGA using Isim software from Xilinx. The result shows that the implementation of 128-bit Advanced Encryption Standard-AES improved considerably the operating speed by 565000 ps for both encryption and decryption process. Similarly, the 233-bit multitive algorithm kP on elliptic curve also enhanced then operating speed at 467661900000 ps. Using above mentioned algorithm, the system maintains the security level meanwhile it does not require very high hardware configuration.

The RFID technology in combination with cryptographic algorithms and protocols is discussed widely as a promising solution against product counterfeiting. Usually the discussion is focussed on passive low-cost RFID-tags, which have harsh power constraints. 4-Bit microcontrollers have very low-power characteristics (5-60 muA) and are therefore an interesting platform for active and passive low-cost RFID-tags. To the best of our knowledge there are no implementations of cryptographic algorithms on a 4-bit microcontroller published so far. Therefore, the main contribution of this work is to demonstrate that cryptography is feasible on these ultra-constrained devices and to close this gap. We chose PRESENT as the cryptographic algorithm, because contrary to many other ciphers, PRESENT uses a 4times4 S-Box. Our implementation draws a current of 6:7 muA at a supply voltage of 1:8 V and a frequency of 500 KHz and requires less than 200 ms for the processing of one data block.

Side-channel analysis (SCA) is launched by exploiting the information leaking from the implementation a cryptographic algorithm, e.g., power consumption information. Recently, deep learning-based SCA techniques have also facilitated SCA against software and hardware implementations of various cryptographic algorithms. In this work, we perform SCA using various deep learning (DL) techniques such as Multi-layered Perceptron (MLP), Convolutional Neural Network (CNN), and Recurrent Neural Network (RNN) on the datasets collected from hardware and software platforms. The objective of this work is to identify the performance of DL techniques in performing SCA for secret key recovery and finding out the best settings for the model to optimize the attack performance in terms of on computation time and SCA efficiency. In our study, we have focused on two open-source AES-128 encryption algorithm databases, ASCAD and DPA contest v2 (DPAv2), where ASCAD database consists of the power traces captured from a software implementation of the AES and DPAv2 database consists of the power traces captured a hardware implementation of the AES. For the first time, we applied hyperparameter tuning with Bayesian Optimization and distributed computing on ASCAD database and we investigated the impact of MLP and RNN along with the distributed computing and hyperparameter tuning with Bayesian optimization on DPAv2 database. Our results show that the CNNs are the best models for performing the attack on software implementation while MLPs are the best for attacking hardware implementation of cryptographic algorithms.

Side Channel Attack (SCA) recovers secret information from an embedded device with implementation of cryptographic algorithm by exploiting its physical leakages. For most SCA methods to achieve good performance, the measured leakages are often desired to be well aligned. However, due to some specific reasons such as inaccurate measurements or carefully designed countermeasures, misalignment of leakages frequently occurs in practice. Misalignment significantly reduces the efficiency of SCA methods, or even makes them fail. To address this issue, two alignment approaches are proposed: a local alignment based on shotgun distance and a global alignment based on weighted edit distance . Compared with previous methods, the proposed methods are capable of keeping the secret dependant leakages, while not introducing any redundant information. In addition, the proposed methods could also reduce the negative effects of noise, which is another factor seriously decreasing the efficiency of SCA methods. Interestingly, it is pretty easy to set appropriate parameters for these two methods. Practical experiments show that the proposed methods outperform previous methods in three different circumstances and different noise levels.

Cloud computing is the outsourcing of communications relevant to IT sector via the use of the internet and maintaining own software and hardware environment.It is an on-demand service facilitated by CSP (Cloud Service Provider).It is available whenever one need it, as much he/she need, and one pays for what he/she use.Security factor is a primary concern of cloud environment.In this research paper along with discussing the basics of cloud computing and the threats involved in a cloud environment, the two main algorithms of cryptography, DES (Data Encryption Standard) and AES (Advanced Encryption Standard) has been elaborated with their individual practical implementation detailing the conversion of plain text to cipher text and vice versa.