Comparative Analysis and Implementation of Cryptographic Algorithms in Cloud Computing

An offline E-cash system is presented that offers appreciably greater security and better privacy than currently considered E-cash system with similar functionality. Most off-line E-cash systems use the temper-resistant IC card which controls an E-cash issued by the card issuer. Offline E-cash system based on IC card has the threats of overspending, double spending, forgery E-cash, altering/eavesdropping transaction contents, etc. To prevent the above threats, there have been a lot of technical discussions of the security requirements for theoretical offline E-cash protocols based on IC card. However, there has been little attention paid to the security requirements for practical offline E-cash system based on IC card including entity authentication, key management, implementation of cryptographic algorithm, etc. Thus, this paper describes the security requirements for cryptographic algorithms, integrity for implementation of cryptographic algorithm, authentication module, key management, and E-cash protocols

Abstract: Cryptographic application plays an important role in wireless communication, especially, a FPGA built-in RFID tag on UHF band (860-960 MHz). The information safety can be obtained by applying suitable and advanced cryptographic algorithm. This paper simulates the installation and implementation of cryptographic algorithm on a FPGA using Isim software from Xilinx. The result shows that the implementation of 128-bit Advanced Encryption Standard-AES improved considerably the operating speed by 565000 ps for both encryption and decryption process. Similarly, the 233-bit multitive algorithm kP on elliptic curve also enhanced then operating speed at 467661900000 ps. Using above mentioned algorithm, the system maintains the security level meanwhile it does not require very high hardware configuration.

The RFID technology in combination with cryptographic algorithms and protocols is discussed widely as a promising solution against product counterfeiting. Usually the discussion is focussed on passive low-cost RFID-tags, which have harsh power constraints. 4-Bit microcontrollers have very low-power characteristics (5-60 muA) and are therefore an interesting platform for active and passive low-cost RFID-tags. To the best of our knowledge there are no implementations of cryptographic algorithms on a 4-bit microcontroller published so far. Therefore, the main contribution of this work is to demonstrate that cryptography is feasible on these ultra-constrained devices and to close this gap. We chose PRESENT as the cryptographic algorithm, because contrary to many other ciphers, PRESENT uses a 4times4 S-Box. Our implementation draws a current of 6:7 muA at a supply voltage of 1:8 V and a frequency of 500 KHz and requires less than 200 ms for the processing of one data block.

Side-channel analysis (SCA) is launched by exploiting the information leaking from the implementation a cryptographic algorithm, e.g., power consumption information. Recently, deep learning-based SCA techniques have also facilitated SCA against software and hardware implementations of various cryptographic algorithms. In this work, we perform SCA using various deep learning (DL) techniques such as Multi-layered Perceptron (MLP), Convolutional Neural Network (CNN), and Recurrent Neural Network (RNN) on the datasets collected from hardware and software platforms. The objective of this work is to identify the performance of DL techniques in performing SCA for secret key recovery and finding out the best settings for the model to optimize the attack performance in terms of on computation time and SCA efficiency. In our study, we have focused on two open-source AES-128 encryption algorithm databases, ASCAD and DPA contest v2 (DPAv2), where ASCAD database consists of the power traces captured from a software implementation of the AES and DPAv2 database consists of the power traces captured a hardware implementation of the AES. For the first time, we applied hyperparameter tuning with Bayesian Optimization and distributed computing on ASCAD database and we investigated the impact of MLP and RNN along with the distributed computing and hyperparameter tuning with Bayesian optimization on DPAv2 database. Our results show that the CNNs are the best models for performing the attack on software implementation while MLPs are the best for attacking hardware implementation of cryptographic algorithms.

This paper presents a single chip efficient FPGA implementation of RSA and DES for Digital Envelope Scheme that targets the Altera Apex 20KE EP20k200EBC356. Implementation of cryptographic algorithms on programmable devices like FPGAs run much faster than on software while preserving physical security of hardware solutions. The high throughput in the implementation of cryptographic algorithms for digital envelope scheme is achieved by means of exploiting the parallelism present in the DES and RSA operations as well as the features of Altera Apex 20KE device family which best suit for system-on-a-programmable-chip (SOPC) applications. The parallelized single chip implementation of DES and RSA for performing the Encryption/Decryption for the Digital envelope scheme offers a throughput of 3.5 Gbits/sec at a system clock rate of 54.7 MHz. This implementation even provides a means for using the DES and RSA separately.

Ensuring security to the information transaction is a major challenge in the communication environment. The choice to guarantee the data transfer using a ciphering algorithm leads to high cost and complexity. The software-based implementations of cryptographic algorithms are easy to design and operate, but the performance penalty paid is high. The hardware implementations of cryptographic algorithms are considered as a task involving intensive computation and evaluation. Microcontroller-based applications for the same prove to be good solutions to the problem for cost-optimized applications. This paper aims to design, implement, and test a microcontroller (AT89c51)-based crypto system using the Tiny Encryption Algorithm and the Extended Tiny Encryption Algorithm as security primitives. The real-time data can be processed with scheduling of the primitives and the context switching between the primitives reduces the probability of being attacked. The keys for the crypto system are generated using internal timers of the microcontroller. The data to be transmitted are encrypted with any one of the security primitives with the generated key and the encrypted data are transmitted both in wired and wireless modes. At the receiving end, the received data are decrypted and the performance of the crypto system is evaluated on the basis of throughput, code size used, and execution time.

Impossible differential cryptanalysis of FBC-128

In today’s world of pervasive computing, all the devices have become smart. The need for securing these devices becomes a need of the hour. The traditional cryptographic algorithms will not be ideal for small devices, and this opens a new area of cryptography named lightweight cryptography, which focuses on the implementation of cryptographic algorithms in resource-constrained devices without compromise in security. Cryptographic hash functions enable detection of message tampering by adversaries. This paper proposes a lightweight hash function that makes use of sponge functions and higher radii hybrid cellular automata (CAs). The proposed hash function shows good cryptographic properties as well as collision resistance and serves as an ideal hash function for lightweight applications.

The design flow of a digital cryptographic device must take into account the evaluation of its security against attacks based on side channels observation. The adoption of high level countermeasures, as well as the verification of the feasibility of new attacks, presently require the execution of time-consuming physical measurements on the prototype product or the simulation at a low abstraction level. Starting from these assumptions, we developed an exploration approach centered on high level simulation, in order to evaluate the actual implementation of a cryptographic algorithm, being it software or hardware based. The simulation is performed within a unified tool based on SystemC, that can model a software implementation running on a microprocessor-based architecture or a dedicated hardware implementation as well as mixed software-hardware implementations with cycle-accurate resolution. Here we describe the tool and provide a large set of design explorations and characterizations based on actual implementations of the AES cryptographic algorithm, demonstrating how the execution of a large set of experiments allowed by the fast simulation engine can lead to important improvements in the knowledge and the identification of the weaknesses in cryptographic algorithm implementations.

In a white-box context, an attacker has full access to the execution environment and the implementation of cryptographic algorithms. Dedicated white-box ciphers, such as WEM and SPNbox, provide incompressibility and key extraction protections in this context, at the cost of increased memory usage and performance loss compared to standard ciphers. Even when a pure white-box threat model is not warranted, the use of incompressible lookup tables can be helpful in deterring side-channel attacks. In this paper we present a simple threat model for such scenarios and propose a dedicated cipher, Space-Hard AES, which provides minimal incompressibility guarantees while presenting better performance for ARMv8 implementations than other dedicated ciphers.

Implementations of cryptographic algorithms are vulnerable to Side-Channel Analyses extracting information from the device behaviour. When such an attack targets the manipulation of several, say d, intermediate variables then it is said to be a d th-order one. A privileged way to circumvent this type of attacks is to split any key-dependent variable into n shares, with n > d, and to adapt the internal processing in order to securely operate on these shares. The latter step is often very tricky and few schemes have been proposed which address this issue in a sound way.At Asiacrypt 2012, Balasch et al. proposed a new scheme based on the inner-product sharing introduced the same year by Dziembowski and Faust at TCC. This scheme is the first one to aim at provable security in two different security models: the continuous bounded-range leakage model and the d th-order side-channel security model (sometimes called d-probing model).In this paper, we contradict the d th-order security claim by exhibiting some first-order information leakages. Namely, we show that some intermediate variables of the scheme depend on secret information whatever the number of shares. This result is of importance since this kind of flaw is considered as a dead-end point when evaluating the practical security of an implementation. To illustrate the effectiveness of the flaw, we perform an information theoretic evaluation of the first-order leakage and we provide simulation results for a standard side-channel attack against the scheme.KeywordsSecret SharingBlock CipherSecurity ModelIntermediate VariableInformation LeakageThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Since side-channel attacks turned out to be a major threat against implementations of cryptographic algorithms, many countermeasures have been proposed. Amongst them, multiplicative blinding is believed to provide a reasonable amount of security for public-key algorithms. In this article we show how template attacks can be used to extract sufficient information to recover the mask. Our practical experiments verify that one power trace suffices in order to remove such a blinding factor. In the course of our work we attacked a protected Montgomery Powering Ladder implementation on a widely used microcontroller. As a result we can state that the described attack could be a serious threat for public key algorithms implemented on devices with small word size.

Side Channel Attack (SCA) recovers secret information from an embedded device with implementation of cryptographic algorithm by exploiting its physical leakages. For most SCA methods to achieve good performance, the measured leakages are often desired to be well aligned. However, due to some specific reasons such as inaccurate measurements or carefully designed countermeasures, misalignment of leakages frequently occurs in practice. Misalignment significantly reduces the efficiency of SCA methods, or even makes them fail. To address this issue, two alignment approaches are proposed: a local alignment based on shotgun distance and a global alignment based on weighted edit distance . Compared with previous methods, the proposed methods are capable of keeping the secret dependant leakages, while not introducing any redundant information. In addition, the proposed methods could also reduce the negative effects of noise, which is another factor seriously decreasing the efficiency of SCA methods. Interestingly, it is pretty easy to set appropriate parameters for these two methods. Practical experiments show that the proposed methods outperform previous methods in three different circumstances and different noise levels.

Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, various schemes to protect cryptographic devices against such attacks have been devised and some implemented in practice. Almost all of these protection schemes target an individual side-channel attack and consequently, it is not obvious whether a scheme for protecting the device against one type of side- channel attacks may make the device more vulnerable to another type of side-channel attacks. We examine in this paper the possibility of such a negative impact for the case where fault detection circuitry is added to a device (to protect it against fault injection attacks) and analyze the resistance of the modified device to power attacks. To simplify the analysis we focus on only one component in the cryptographic device (namely, the S-box in the AES and Kasumi ciphers), and perform power attacks on the original implementation and on a modified implementation with an added parity check circuit. Our results show that the presence of the parity check circuitry has a negative impact on the resistance of the device to power analysis attacks.

AEGIS, a dedicated authenticated encryption algorithm is one of the winners of the CAESAR portfolio. In literature, there exist fault attacks on AEGIS family of ciphers. Fault attack is one of the most efficient forms of side-channel attacks against implementations of cryptographic algorithms, and the protection against fault attack is vital for security-related devices. In this paper, we propose countermeasures for AEGIS family of ciphers. The proposed countermeasures show that the state of the ciphers can not be recovered faster than exhaustive search because it needs \(2^{128}\) time to recover a state of each cipher.KeywordsAuthenticated encryptionFault attackCountermeasuresCAESARAES