Block Level SoC Verification Using Systemverilog

Today’s scenario of semiconductor technology is a tremendous innovation; it includes a large number of intellectual property (IP) cores, interconnects, or buses in system on chip (SOC) design and based upon the necessity its complexity keeps on increasing. Hence, for the communication between these IP cores, a standard protocol is developed. The necessity of IP reuse, abridging the design time and the complexity makes large-scale SOC more challenging in order to endorse IP core reusability for SOC designs. An efficient non-proprietary protocol for communication between IP cores is open core protocol (OCP). OCP comes under socket-based interface and openly licensed core concentric protocol. This paper addresses on the verification of implemented design of OCP. The proposed paper is to verify the implemented design by using System Verilog and Universal Verification Methodology (UVM) in SimVision tool.

This paper discusses a generic flow on how an automated SV-based test bench environment which is randomized with constraints can verify a SOC effectively for its functionality and code coverage [1]. Today, in the era of multimillion gate ASICs, reusable intellectual property (IP), and system-on-a-chip (SoC) designs, verification [1] consumes about 70 % of the design effort. Automation lets you do something else while a machine completes a task autonomously, faster and with predictable results. Automation requires standard processes with well-defined inputs and outputs. Not all processes can be automated. Because of the variety of functions, interfaces, protocols, and transformations that must be verified, it is not possible to provide a general purpose automation solution for verification, given today’s technology. It is possible to automate some portion of the verification process, especially when applied to a narrow application domain. Tools automating various portions of the verification process are being introduced. Here, we have a SOC with a ARM multicore processor which talks to one of the peripherals, which is a flash memory (CODE FLASH and a DATA FLASH). The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence OVM libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the methodology [2] implemented in system verilog for SOC verification.

The challenges of system on a chip (SoC) verification is becoming increasingly complex as submicron process technology shrinks die size, enabling system architects to include more functionality in a single chip solution. A functional defect refers to the feature sets, protocols or performance parameters not conforming to the specifications of the SoC. Some of the functional defects can be solved by software workarounds but some require revisions of silicon. The revision of silicon not only costs millions of dollars but also impacts time to market, quality, customer commitments. Working silicon for the first revision of the SoC requires a robust module, chip and system verification strategy to uncover the logical and timing defects before tapeout. Different techniques are needed at each level (module, chip and system) to complete verification. In addition verification should quantify with a metric at every hierarchy to assess functional holes and address it. Verification metric can be a combination of code coverage, functional coverage, assertion coverage, protocol coverage, interface coverage and system coverage. A successful verification strategy also requires the test bench to be scalable, configurable, support reuse of functional tests, integration with tools and finally linkage to validation. The scope of this paper will discuss the verification strategy and pitfalls used in verification strategy and finally make recommendations for successful strategy.

Design complexity is ever increasing with multi- mode, statistical timing analysis, multi-vt/VDD low power and multi-core performance based type of designs. IEEE 1800 system verilog (Ref 1) is a natural smooth transition language to verilog (Refi and 3) for system level design and verification. Verilog RTL has been popularly used for many design tape outs. System verilog (SV) extensive support exists in verification tools viz. simulators, formal for various powerful SV specific design constructs. It is envisaged that SV will be used for design tape outs soon as many design houses started using SV specific RTL constructs for system designs involving high levels of design data abstractions for various design application keeping in view of verification support. This paper analyzes on various SV design specific constructs for design quality of results (QOR) improvement. The specific constructs discussed for design QOR improvements are 1) operator overloading using user defined types to bring in efficient implementation of data path operators like multiplier, adder, shift,.. 2) Parameterized module interface for different sized datapath, memory, fifo, register files.. 3) Configuration to bind a particular efficient architecture to a module based on QOR requirement 4) System level modules interface and arbitration using "interface"construct. 5) Multiple clock domain definition and interface. 6) IEEE1801 UPF low power design intent flow.

Verification demands for system on chip (SoC) design looms as one of the most significant challenges to designers. With the substantial costs and increasing importance of system verification technologies, determining the best verification strategy is critical to SoC design and business success. The paper focuses on how a designer can apply a model to perform tradeoffs between the different types of emulation, hardware acceleration, and simulation verification tools available. The predictive power of the modeling approach is applied to usage scenarios to determine the most appropriate verification strategy to employ in current or future SoC development efforts.

Abstract—The Advanced High-performance Bus (AHB), a key component of the Advanced Microcontroller Bus Architecture (AMBA) family, stands as a high-performance, low-power, and high- bandwidth communication interface within system components. Bridging to low-bandwidth peripherals, the Advanced Peripheral Bus (APB) offers a simple, non-pipelined protocol for read- and-write communication, linking a bridge/master to numerous slaves via a shared bus. The AHB to APB bridge serves a critical role in integrating diverse bus protocols, facilitating efficient communication between high-performance processing units and slower peripherals, thereby enhancing the System-on-Chip (SoC)'s overall effectiveness and functionality. This approach addresses the functional verification of the AMBA AHB to APB Bridge protocol with a focus on completeness. We employ a layered testbench architecture in System Verilog to ensure thorough verification of functionality with maximal coverage. Our verification environment is constructed using System Verilog, and simulations are conducted on the EDA playground platform. Through this comprehensive approach, we aim to provide robust validation of the AHB to APB bridge protocol, ensuring its reliability and compatibility within complex SoC designs. Keywords— Advanced Peripheral Bus (APB), System-On-Chip (SOC), Advanced Microcontroller Bus Architecture.

As modern System-on-chip (SoC) designs grow in complexity, traditional debug mechanisms involving manual waveform and log analysis struggle to keep up with the volume and intricacies of failures. Complex SoCs integrate multiple application-specific processors posing a challenge in the debugging phase of Design Verification (DV) and Post-Silicon Validation (PSV). We propose Artificial Intelligence (AI) augmented verification strategies to enhance debugging and improve verification efficiency. The proposed work uses Deep learning models alongside SystemVerilog (SV) based assertions in test bench (TB) and Python routines. By leveraging the capability of Recurrent Neural Networks (RNN) to remember sequential data, we attempt to simplify the bus protocol error debug in DV. We observe that the Long short-term memory (LSTM) algorithm consistently outperforms the RNN algorithm in terms of accuracy in bus error detection and classification. LSTM Autoencoder is used for anomaly detection in waveform mining, which is then used to identify required TB or design updates through Python routine. An integrated dashboard improves the efficacy of using this AI-Machine Learning (ML) based solution for debugging. Overall, with this approach, we observed that verification effort became 0.54x.

System on Chip (SoC) designs inherit all the well known verification and validation difficulties associated with complex ASIC designs, besides adding their own set of newer problems. These arise because SoCs are primarily implemented by re-using Intellectual Property (IP) cores. It is well known that verification today constitutes about 70% to 80% of the total design effort, thereby, making it the most expensive component in terms of cost and time, in the entire design flow. It is expected to get even worse for SoC designs. In a complex SoC design flow functional verification is very important; any behavioral or functional bug escaping this phase will not be detected in the subsequent implementation phases and will surface only after the first silicon is integrated into the target system, resulting in costly design and silicon iterations. A number of academic and industrial research laboratories have been carrying out research on functional verification of SoCs based on different approaches. Partial success has been achieved in deploying them. Many of the issues relate to intrinsic limitations of some of the approaches taken; while others have to do with the quality of the design information, by way of, design descriptions, design documentations and design specifications, from which the overall verification objectives are derived. SoCs have brought to focus the need to carry out design and verification concurrently. For the design and verification task to proceed concurrently there is a need to capture formally, design information and implementation details at various levels of abstraction. Another reason for the need to formalize is that, as designs become more complex, functional verification will have to be carried out using the divide and conquer approach.We discuss several approaches based on compositional verification. For these approaches to succeed, specifications of either, the individual modules, or individual IPs, if any are used, have to be stated formally. There exist several commercial offerings addressing the area of SoC functional verification. Most of these use some form of divide and conquer approach related to compositional verification. The basis of success of some of these tools lies in the fact that the specifications of the IP cores are in essence captured in some executable form, be they formal specification languages, or commonly used HDLs suitably modified for the purpose.This tutorial is structured to provide information on the state of the art in the area of functional verification. It will focus on existing methodologies, tools, and practical approaches based on universal simulation, emulation, formal verification, and semi-formal verification that can be employed to overcome the SoC verification problem. We discuss a number of real life verification projects, describing the various techniques used and the effectiveness of these techniques. We conclude the tutorial by presenting issues, which form the current focus for research.

Modern day system-on-chip (SoC) designs have many inbuilt IP cores and it is crucial that the communication between these cores is properly synchronized. This synchronization is ensured by the interconnects based on various bus protocols. Hence, it is crucial to verify these interconnects during the development of such SoCs and this is what takes most of the time as compared to the design stage. But writing test benches each time to verify various protocols would be time consuming, challenging and requires deep knowledge of these protocols and methodology expertise. So nowadays, configurable test benches are used which helps eliminating tedious tasks of developing tests for complex protocols. A test suite is a complete self-contained, configurable environment targeted at the verification of interconnects used in complex SoCs. It is a collection of test cases and sequences written in a generic way aimed at reducing the time for verification. It simplifies integration, enables user customization, and maximizes reuse across projects. This paper shows how the test suite addresses the challenges faced during the verification of interconnects used in complex SoCs. It also involves writing an example test suite sequence and test using the Universal Verification Methodology (UVM) which is a standard verification methodology based on the System Verilog language.

The high efficiency is demanded in aerospace field. In the design of the control system, adopting single processor can hardly meet the demand of efficiency required. However processor array's hardware size and off-chip bus delay cannot be ignored. In order to solve the above mentioned problems, this paper is intended to study multi-task collaborative parallel design based on multi-core SOC (system on chip). Firstly, multi-core architecture based on SOC is achieved, which includes constructing two MicroBlaze cores, two ARM (advanced RISC machines) cores and designing inter-core communication, as well as designing external data collection and hardware acceleration unit based on FPGA (field programmable gate array). Secondly, collaborative parallel design in missile control system is studied. Finally, a verification platform is developed. By comparing with single core processor, it is proved that the approaches proposed have advantages over enhancing the efficiency.

In a SoC (system-on-chip) design, a design complexity is a big bottleneck. In order to overcome the design complexity, platform based design method is widely adopted for designers. Most complex SoCs need a heterogeneous design development environment for hardware and software co-design. In this paper, we discuss about some kinds of verification approaches with platform based design methodology at various abstraction levels of SoC design. We separate the verification process to two steps according to the different levels of verification. We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.

This paper describes a FPGA-based verification methodology for the image signal processor (ISP) of system-on-chip (SoC) type CMOS image sensor. To make a verification environment, the complete ASIC prototyping system, the ARM7 TDMI CoreTile board and external interface boards — the sensor board, the USB board and the switch board — are used. As a verification method, 4-step verification strategy comprised of ARM-core based platform verification, system verification, algorithm verification and performance verification is used. Through this method, the 2M-pixel/3M-pixel ARM-based ISP of CMOS image sensor is verified very effectively before tape-out.

Verification activities are intended to reduce the costs of system development by identifying design errors before deploying the system. However, subcontractors in multifirm projects are motivated to implement locally cost‐effective verification strategies over verification strategies that benefit the main contractor. Incentivizing verification activities is one mechanism by which the contractor can motivate subcontractors to implement verification strategies desirable to the contractor. Prior work on mathematical models of verification in systems engineering has neither explored optimal verification strategies nor incentives in multi‐firm projects. In this paper, we present a modeling concept for determining optimal verification strategies in multi‐firm projects. Our models are belief‐based, which means that contractors and subcontractors incorporate their at times limited knowledge about true verification state through a probabilistic assessment of possible states. We develop an initial two‐level model, where one contractor directly works with multiple subcontractors at the next lower level. This model is then extended to a general network model with multiple, multilevel contractor‐subcontractor relationship. We derive solution algorithms that characterize the optimal verification strategies and incentives for each of the firms. Our work contributes to the systems engineering literature by laying the foundation for the study of incentives as a mechanism to align verification activities in multi‐firm systems engineering projects.

System-on-Chip (SoC) Verification is becoming a challenge in nowadays chips. Hardware acceleration is becoming mandatory in SoC verification. Emulation enables longer test cases and more tests to run in less time. However, emulation based verification is still not supporting verification of analog modules. These analog modules are parts of the Physical Layer (PHY) of the Designs-Under-Test (DUT) which includes some digital modules as well to interface with upper layers in the protocol and to control analog modules. So, there is a need to develop emulator friendly physical layers of different protocols to enable emulation based verification. These PHY modules should be flexible enough to cover different configurations of the designs under test. This paper presents how to enable emulation based verification of a full Serial ATA protocol (SATA) controller designs, used in storage applications, using a SATA Verification IP (VIP) and Configurable SATA PHY design.

The SoC (System on Chip) uses AMBA (Advanced Microcontroller Bus Architecture) as an on chip bus. APB (Advanced Peripheral Bus) is one of the components of the AMBA bus architecture. APB is low bandwidth and low performance bus used to connect the peripherals like UART, Keypad, Timer and other peripheral devices to the bus architecture. This paper introduces the AMBA APB bus architecture design. The design is created using the verilog HDL and is tested by a System verilog test- bench. This design is verified using SV. A reuse based methodology for SoC design has become essential in order to meet these challenges. The work embodied in this paper presents the design of APB Protocol and the Verification of slave APB Protocol. Coverage analysis is a vital part of the verification process; it gives idea that to what degree the source code of the DUT has been tested. The functional coverage analysis increases the verification efficiency enabling the verification engineer to isolate the areas of untested function. The design and verification IP is built by developing verification components using Verilog and System Verilog respectfully with relevant tools such as Questasim and Cadence, which provides the suitable building blocks to design the test environment.