Optimal verification strategies in multi‐firm projects

This paper proposes a set of seven elemental patterns of verification strategies. These patterns can be useful in modeling verification strategies in a wide range of engineered systems. They form the building blocks under which any verification strategy can be modeled. The patterns lead to a fundamental understanding of the interplay between system parameters and verification activities, as well as an understanding of the mechanisms by which verification evidence builds up. For each pattern, we provide a description and a few examples of its application. A few important theoretical properties of the corresponding set of patterns are discussed, such as belief update, inferential properties, and graph disconnection, as well as some practical guidance to be taken into account when applying them to authentic verification problems. These patterns are intended to be a useful tool for researchers, practitioners, and educators, by formalizing the application of Bayesian networks to verification problems, hence facilitating instruction and communication among verification engineers and with researchers from other domains, particularly statisticians and Bayesian analysts.

In current practice, a verification strategy (VS) is planned by considering various uncertainties at the beginning of a development program. All relevant uncertainties are expected to be calibrated to facilitate the evaluation of the planned verification strategies. However, not all calibration information about uncertainties may be available at the beginning and some additional activities to discover unknown uncertainties may be necessary. This paper presents a set‐based planning (SBP) methodology for designing and executing system verification strategies under knowable uncertainty (KU). Building on a Bayesian network model of verification and correction activities (CAs), we introduce preparation activities that quantify KU, enabling dynamic planning as new information becomes available. Using a notional satellite communication instrument as a case study, we compare SBP against traditional static planning across scenarios with varying estimation errors in likelihood ratio (LR) values. Results show that SBP consistently achieves higher expected values, with substantial gains when CAs have low success rates. The findings provide practical guidance on when dynamic verification planning yields value and lay the groundwork for extensions to broader classes of uncertainty.

The challenges of system on a chip (SoC) verification is becoming increasingly complex as submicron process technology shrinks die size, enabling system architects to include more functionality in a single chip solution. A functional defect refers to the feature sets, protocols or performance parameters not conforming to the specifications of the SoC. Some of the functional defects can be solved by software workarounds but some require revisions of silicon. The revision of silicon not only costs millions of dollars but also impacts time to market, quality, customer commitments. Working silicon for the first revision of the SoC requires a robust module, chip and system verification strategy to uncover the logical and timing defects before tapeout. Different techniques are needed at each level (module, chip and system) to complete verification. In addition verification should quantify with a metric at every hierarchy to assess functional holes and address it. Verification metric can be a combination of code coverage, functional coverage, assertion coverage, protocol coverage, interface coverage and system coverage. A successful verification strategy also requires the test bench to be scalable, configurable, support reuse of functional tests, integration with tools and finally linkage to validation. The scope of this paper will discuss the verification strategy and pitfalls used in verification strategy and finally make recommendations for successful strategy.

Verification planning is a sequential decision-making problem that specifies a set of verification activities (VAs) and correction activities (CAs) at different phases of system development. While VAs are used to identify errors and defects, CAs also play important roles in system verification as they correct the identified errors and defects. However, current planning methods only consider VAs as decision choices. Because VAs and CAs have different activity spaces, planning a joint verification-correction strategy (JVCS) is challenging, especially for large-scale systems. Here, we introduce a UCB-based tree search approach to search for near-optimal JVCSs. First, verification planning is simplified as repeatable bandit problems and an upper confidence bound rule for repeatable bandits (UCBRBs) is presented with the optimal regret bound. Next, a tree search algorithm is proposed to search for feasible JVCSs. A tree-based ensemble learning model is also used to extend the tree search algorithm to handle local optimality issues. The proposed approach is evaluated on the notional case of a communication system.

We demonstrate a new modelling technique that facilitates the description and the formal verification of timing properties of concurrent systems, such as asynchronous digital hardware. We utilise a process algebra and its associated automatic verification system and construct models and verification strategies using them. Utilising the hierarchical nature of our approach, these techniques may then be applied to larger systems, such as asynchronous circuits of commercial complexity. The modelling techniques introduced permit four distinct classes of objects, namely system components, assumed constraints on their behaviour, properties requiring proof and behaviour refinements, all to be modelled by a process. We illustrate this approach by modelling the necessary timing relationships required for the correct operation of asynchronous micropipline stages and then verifying that the resulting behaviour is correct. Finally, we demonstrate how the same models are used to make some observations about the performance and the timing properties of such designs.

Reactive systems are often modelled as two person antagonistic games where one player represents the system while his adversary represents the environment. Undoubtedly, the most popular games in this context are parity games and their cousins (Rabin, Streett and Muller games). Recently however also games with other types of payments, like discounted or mean-payoff [5,6], previously used only in economic context, entered into the area of system modelling and verification. The most outstanding property of parity, mean-payoff and discounted games is the existence of optimal positional (memoryless) strategies for both players. This observation raises two questions: (1) can we characterise the family of payoff mappings for which there always exist optimal positional strategies for both players and (2) are there other payoff mappings with practical or theoretical interest and admitting optimal positional strategies. This paper provides a complete answer to the first question by presenting a simple necessary and sufficient condition on payoff mapping guaranteeing the existence of optimal positional strategies. As a corollary to this result we show the following remarkable property of payoff mappings: if both players have optimal positional strategies when playing solitary one-player games then also they have optimal positional strategies for two-player games.

Signatures are commonly used as a unique way of identifying and verifying a person’s identity. Legal documents like bank cheques and transactions, government documents, and affidavits require signature-based verification to identify the authenticity of the person. The signature identification and verification system help to distinguish whether an input signature is honest or a fake. For very long years, this was considered to be a challenging mission when the offline mode was taken into consideration. The offline mode uses scanned signature images, where the online mode of signing process isn't existing. To overcome the signature verification challenge, an application of deep learning techniques to identify feature representations from signature images can be leveraged. In this paper, we have demonstrated how to identify valid and invalid signatures by building a signature verification and identification system that uses deep convolution neural network (ConvNet).KeywordsDeep learningConvolution neural network (ConvNet)Signature verification

Deriving verification objectives and scenarios for maritime systems using the systems-theoretic process analysis

This paper presents an automatic video based face verification and recognition system by Support Vector Machines (SVMs). Faces as training samples are automatically extracted from input video sequences in real-time by LUT-based Adaboost and are normalized both in geometry and in gray level distribution after facial landmark localization via Simple Direct Appearance Model (SDAM). Two different strategies for multi-class face verification and recognition problems with SVMs, one-vs-all and one-vs-another, are discussed and compared in details. Experiment results over 100 clients are reported to demonstrate the effectiveness of SVM on video sequences.

Due to the rapid advances in algorithms, VLSI design and computer technology, security systems based on speaker recognition are on the verge of commercial success. In this thesis, an improved strategy for Text Tndependent Automatic Speaker Verification (TI-ASV) system based on Malayalam has been proposed and results are observed. The system performs on Gaussian Mixture Model (GMM) technique with cepstral based features. Different speech pre-processing techniques like pre-emphasis filtering, frame blocking and windowing have been used to process the speech utterances. MFCC, ΔMFCC and ΔΔMFCC have been used to extract the features. Speaker identification is performed using Continuous Hidden Markov Model. The performance is analyzed in terms of Percentage Correctness (PC) and accuracy. An application with Graphical User Interface (GUI) is also developed for security purposes using the system. The system is developed using the framework of Hidden Markov Model Tool Kit (HTK).

System verification and validation are important activities in the software development process aiming at testing the software system in various quality aspects. The purpose is to investigate the important characteristics of the verification and validation activities in the software development process in an organization. A qualitative research method is employed in order to facilitate the assessment and understanding of a testing key area regarding the software development process. The methodology and results could act as input to other organizations, which are likely to have other important characteristics than the ones included in this study. The main characteristics were identified in the analysis and it was concluded that the results could facilitate further process improvements in the organization.

SAFE-V launcher validation framework and controller optimization

Unified Modeling Language is being used for modeling of business processes, real-time systems, embedded systems and hybrid systems. In software engineering, there are different techniques for verification of such systems. Model checking is one of the techniques for the automatic verification of software models. Earlier, these model were verified by sequential model checking tools. For very large complex systems, parallel verification can save verification time. DiVinE is a model checking tool for both CPUs and GPUs clusters to perform parallel linear time logic (LTL) verification of systems. In this paper, we propose a parallel verification methodology for UML models using DiVinE tool. We explain this methodology by the case study example of fuel filling machine.

Introducing a new strategy for verification of System On Chip (SoC) using system Verilog. System Verilog provides a great platform for verification. The OOPs concept in System Verilog make it more reliable. There are many existing SoC verification methods are available. But most of them are not that much efficient. So here we are planning to introduce a new verification strategy that takes many of the positive characteristics of the existing strategies and mixes them together to have an efficient and perfect strategy by using the advantages of System Verilog.

Verification demands for system on chip (SoC) design looms as one of the most significant challenges to designers. With the substantial costs and increasing importance of system verification technologies, determining the best verification strategy is critical to SoC design and business success. The paper focuses on how a designer can apply a model to perform tradeoffs between the different types of emulation, hardware acceleration, and simulation verification tools available. The predictive power of the modeling approach is applied to usage scenarios to determine the most appropriate verification strategy to employ in current or future SoC development efforts.